1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38import m5
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38import m5
|
| 39import _m5
|
39from m5.objects import *
40m5.util.addToPath('../configs/')
41from common.Caches import *
42
43class Sequential:
44 """Sequential CPU switcher.
45
46 The sequential CPU switches between all CPUs in a system in
47 order. The CPUs in the system must have been prepared for
48 switching, which in practice means that only one CPU is switched
49 in. base_config.BaseFSSwitcheroo can be used to create such a
50 system.
51 """
52 def __init__(self, cpus):
53 self.first_cpu = None
54 for (cpuno, cpu) in enumerate(cpus):
55 if not cpu.switched_out:
56 if self.first_cpu != None:
57 fatal("More than one CPU is switched in");
58 self.first_cpu = cpuno
59
60 if self.first_cpu == None:
61 fatal("The system contains no switched in CPUs")
62
63 self.cur_cpu = self.first_cpu
64 self.cpus = cpus
65
66 def next(self):
67 self.cur_cpu = (self.cur_cpu + 1) % len(self.cpus)
68 return self.cpus[self.cur_cpu]
69
70 def first(self):
71 return self.cpus[self.first_cpu]
72
73def run_test(root, switcher=None, freq=1000, verbose=False):
74 """Test runner for CPU switcheroo tests.
75
76 The switcheroo test runner is used to switch CPUs in a system that
77 has been prepared for CPU switching. Such systems should have
78 multiple CPUs when they are instantiated, but only one should be
79 switched in. Such configurations can be created using the
80 base_config.BaseFSSwitcheroo class.
81
82 A CPU switcher object is used to control switching. The default
83 switcher sequentially switches between all CPUs in a system,
84 starting with the CPU that is currently switched in.
85
86 Unlike most other test runners, this one automatically configures
87 the memory mode of the system based on the first CPU the switcher
88 reports.
89
90 Keyword Arguments:
91 switcher -- CPU switcher implementation. See Sequential for
92 an example implementation.
93 period -- Switching frequency in Hz.
94 verbose -- Enable output at each switch (suppressed by default).
95 """
96
97 if switcher == None:
98 switcher = Sequential(root.system.cpu)
99
100 current_cpu = switcher.first()
101 system = root.system
102 system.mem_mode = type(current_cpu).memory_mode()
103
104 # Suppress "Entering event queue" messages since we get tons of them.
105 # Worse yet, they include the timestamp, which makes them highly
106 # variable and unsuitable for comparing as test outputs.
| 40from m5.objects import *
41m5.util.addToPath('../configs/')
42from common.Caches import *
43
44class Sequential:
45 """Sequential CPU switcher.
46
47 The sequential CPU switches between all CPUs in a system in
48 order. The CPUs in the system must have been prepared for
49 switching, which in practice means that only one CPU is switched
50 in. base_config.BaseFSSwitcheroo can be used to create such a
51 system.
52 """
53 def __init__(self, cpus):
54 self.first_cpu = None
55 for (cpuno, cpu) in enumerate(cpus):
56 if not cpu.switched_out:
57 if self.first_cpu != None:
58 fatal("More than one CPU is switched in");
59 self.first_cpu = cpuno
60
61 if self.first_cpu == None:
62 fatal("The system contains no switched in CPUs")
63
64 self.cur_cpu = self.first_cpu
65 self.cpus = cpus
66
67 def next(self):
68 self.cur_cpu = (self.cur_cpu + 1) % len(self.cpus)
69 return self.cpus[self.cur_cpu]
70
71 def first(self):
72 return self.cpus[self.first_cpu]
73
74def run_test(root, switcher=None, freq=1000, verbose=False):
75 """Test runner for CPU switcheroo tests.
76
77 The switcheroo test runner is used to switch CPUs in a system that
78 has been prepared for CPU switching. Such systems should have
79 multiple CPUs when they are instantiated, but only one should be
80 switched in. Such configurations can be created using the
81 base_config.BaseFSSwitcheroo class.
82
83 A CPU switcher object is used to control switching. The default
84 switcher sequentially switches between all CPUs in a system,
85 starting with the CPU that is currently switched in.
86
87 Unlike most other test runners, this one automatically configures
88 the memory mode of the system based on the first CPU the switcher
89 reports.
90
91 Keyword Arguments:
92 switcher -- CPU switcher implementation. See Sequential for
93 an example implementation.
94 period -- Switching frequency in Hz.
95 verbose -- Enable output at each switch (suppressed by default).
96 """
97
98 if switcher == None:
99 switcher = Sequential(root.system.cpu)
100
101 current_cpu = switcher.first()
102 system = root.system
103 system.mem_mode = type(current_cpu).memory_mode()
104
105 # Suppress "Entering event queue" messages since we get tons of them.
106 # Worse yet, they include the timestamp, which makes them highly
107 # variable and unsuitable for comparing as test outputs.
|
107 m5.internal.core.cvar.want_info = verbose
| 108 _m5.core.cvar.want_info = verbose
|
108
109 # instantiate configuration
110 m5.instantiate()
111
112 # Determine the switching period, this has to be done after
113 # instantiating the system since the time base must be fixed.
114 period = m5.ticks.fromSeconds(1.0 / freq)
115 while True:
116 exit_event = m5.simulate(period)
117 exit_cause = exit_event.getCause()
118
119 if exit_cause == "simulate() limit reached":
120 next_cpu = switcher.next()
121
122 if verbose:
123 print "Switching CPUs..."
124 print "Next CPU: %s" % type(next_cpu)
125 m5.drain()
126 if current_cpu != next_cpu:
127 m5.switchCpus(system, [ (current_cpu, next_cpu) ],
128 verbose=verbose)
129 else:
130 print "Source CPU and destination CPU are the same, skipping..."
131 current_cpu = next_cpu
132 elif exit_cause == "target called exit()" or \
133 exit_cause == "m5_exit instruction encountered":
134
135 sys.exit(0)
136 else:
137 print "Test failed: Unknown exit cause: %s" % exit_cause
138 sys.exit(1)
| 109
110 # instantiate configuration
111 m5.instantiate()
112
113 # Determine the switching period, this has to be done after
114 # instantiating the system since the time base must be fixed.
115 period = m5.ticks.fromSeconds(1.0 / freq)
116 while True:
117 exit_event = m5.simulate(period)
118 exit_cause = exit_event.getCause()
119
120 if exit_cause == "simulate() limit reached":
121 next_cpu = switcher.next()
122
123 if verbose:
124 print "Switching CPUs..."
125 print "Next CPU: %s" % type(next_cpu)
126 m5.drain()
127 if current_cpu != next_cpu:
128 m5.switchCpus(system, [ (current_cpu, next_cpu) ],
129 verbose=verbose)
130 else:
131 print "Source CPU and destination CPU are the same, skipping..."
132 current_cpu = next_cpu
133 elif exit_cause == "target called exit()" or \
134 exit_cause == "m5_exit instruction encountered":
135
136 sys.exit(0)
137 else:
138 print "Test failed: Unknown exit cause: %s" % exit_cause
139 sys.exit(1)
|