1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38import m5
39import _m5
40from m5.objects import *
41m5.util.addToPath('../configs/')
42from common.Caches import *
43
44class Sequential:
45 """Sequential CPU switcher.

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117 while True:
118 exit_event = m5.simulate(period)
119 exit_cause = exit_event.getCause()
120
121 if exit_cause == "simulate() limit reached":
122 next_cpu = switcher.next()
123
124 if verbose:
125 print "Switching CPUs..."
126 print "Next CPU: %s" % type(next_cpu)
127 m5.drain()
128 if current_cpu != next_cpu:
129 m5.switchCpus(system, [ (current_cpu, next_cpu) ],
130 verbose=verbose)
131 else:
132 print "Source CPU and destination CPU are the same, skipping..."
133 current_cpu = next_cpu
134 elif exit_cause == "target called exit()" or \
135 exit_cause == "m5_exit instruction encountered":
136
137 sys.exit(0)
138 else:
139 print "Test failed: Unknown exit cause: %s" % exit_cause
140 sys.exit(1)