smmu_v3_cmdexec.cc (14065:f925f90bda01) | smmu_v3_cmdexec.cc (14104:b2c26dc6f20e) |
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1/* 2 * Copyright (c) 2013, 2018-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51 a.ifc = nullptr; 52 a.delay = 0; 53 yield(a); 54 55 while (true) { 56 busy = true; 57 58 while (true) { | 1/* 2 * Copyright (c) 2013, 2018-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51 a.ifc = nullptr; 52 a.delay = 0; 53 yield(a); 54 55 while (true) { 56 busy = true; 57 58 while (true) { |
59 int sizeMask = mask(smmu.regs.cmdq_base & Q_BASE_SIZE_MASK); | 59 // Masking depending on CMDQ_BASE.LOG2SIZE (log(number of 60 // queue entries)). Example: a value of 0b101 (32 entries) 61 // generates a 0b11111 mask. 62 int size_mask = mask( 63 smmu.regs.cmdq_base & Q_BASE_SIZE_MASK); |
60 | 64 |
61 if ((smmu.regs.cmdq_cons & sizeMask) == 62 (smmu.regs.cmdq_prod & sizeMask)) | 65 // In this case the wrap bit is considered (+1) 66 int size_mask_wrap = mask( 67 (smmu.regs.cmdq_base & Q_BASE_SIZE_MASK) + 1); 68 69 if ((smmu.regs.cmdq_cons & size_mask_wrap) == 70 (smmu.regs.cmdq_prod & size_mask_wrap)) |
63 break; // command queue empty 64 | 71 break; // command queue empty 72 |
65 Addr cmdAddr = | 73 Addr cmd_addr = |
66 (smmu.regs.cmdq_base & Q_BASE_ADDR_MASK) + | 74 (smmu.regs.cmdq_base & Q_BASE_ADDR_MASK) + |
67 (smmu.regs.cmdq_cons & sizeMask) * sizeof(SMMUCommand); | 75 (smmu.regs.cmdq_cons & size_mask) * sizeof(SMMUCommand); |
68 69 // This deliberately resets the error field in cmdq_cons! | 76 77 // This deliberately resets the error field in cmdq_cons! |
70 smmu.regs.cmdq_cons = (smmu.regs.cmdq_cons + 1) & sizeMask; | 78 smmu.regs.cmdq_cons = (smmu.regs.cmdq_cons + 1) & size_mask_wrap; |
71 | 79 |
72 doRead(yield, cmdAddr, &cmd, sizeof(SMMUCommand)); | 80 doRead(yield, cmd_addr, &cmd, sizeof(SMMUCommand)); |
73 smmu.processCommand(cmd); 74 } 75 76 busy = false; 77 // No more commands to process, signal the SMMU as drained 78 smmu.signalDrainDone(); 79 80 doSleep(yield); 81 } 82} | 81 smmu.processCommand(cmd); 82 } 83 84 busy = false; 85 // No more commands to process, signal the SMMU as drained 86 smmu.signalDrainDone(); 87 88 doSleep(yield); 89 } 90} |