1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51 a.ifc = nullptr;
52 a.delay = 0;
53 yield(a);
54
55 while (true) {
56 busy = true;
57
58 while (true) {
59 int sizeMask = mask(smmu.regs.cmdq_base & Q_BASE_SIZE_MASK);
60
61 if ((smmu.regs.cmdq_cons & sizeMask) ==
62 (smmu.regs.cmdq_prod & sizeMask))
63 break; // command queue empty
64
65 Addr cmdAddr =
66 (smmu.regs.cmdq_base & Q_BASE_ADDR_MASK) +
67 (smmu.regs.cmdq_cons & sizeMask) * sizeof(SMMUCommand);
68
69 // This deliberately resets the error field in cmdq_cons!
70 smmu.regs.cmdq_cons = (smmu.regs.cmdq_cons + 1) & sizeMask;
71
72 doRead(yield, cmdAddr, &cmd, sizeof(SMMUCommand));
73 smmu.processCommand(cmd);
74 }
75
76 busy = false;
77 // No more commands to process, signal the SMMU as drained
78 smmu.signalDrainDone();
79
80 doSleep(yield);
81 }
82}