mmapped_ipr.hh (8229:78bf55f23338) mmapped_ipr.hh (8748:01be402c5bf1)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 34 unchanged lines hidden (view full) ---

43#include "mem/packet.hh"
44
45namespace SparcISA
46{
47
48inline Tick
49handleIprRead(ThreadContext *xc, Packet *pkt)
50{
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 34 unchanged lines hidden (view full) ---

43#include "mem/packet.hh"
44
45namespace SparcISA
46{
47
48inline Tick
49handleIprRead(ThreadContext *xc, Packet *pkt)
50{
51#if FULL_SYSTEM
52 return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
51 return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
53#else
54 panic("Shouldn't have a memory mapped register in SE\n");
55#endif
56}
57
58inline Tick
59handleIprWrite(ThreadContext *xc, Packet *pkt)
60{
52}
53
54inline Tick
55handleIprWrite(ThreadContext *xc, Packet *pkt)
56{
61#if FULL_SYSTEM
62 return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
57 return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
63#else
64 panic("Shouldn't have a memory mapped register in SE\n");
65#endif
66}
67
68
69} // namespace SparcISA
70
71#endif
58}
59
60
61} // namespace SparcISA
62
63#endif