mem.cc (7279:157b02cc0ba1) mem.cc (7291:2d21be52e57f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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57 ss << ", ";
58 printReg(ss, op1);
59 ss << ", [";
60 printReg(ss, base);
61 ss << "]";
62 return ss.str();
63}
64
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 48 unchanged lines hidden (view full) ---

57 ss << ", ";
58 printReg(ss, op1);
59 ss << ", [";
60 printReg(ss, base);
61 ss << "]";
62 return ss.str();
63}
64
65string
66RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
67{
68 stringstream ss;
69 switch (mode) {
70 case DecrementAfter:
71 printMnemonic(ss, "da");
72 break;
73 case DecrementBefore:
74 printMnemonic(ss, "db");
75 break;
76 case IncrementAfter:
77 printMnemonic(ss, "ia");
78 break;
79 case IncrementBefore:
80 printMnemonic(ss, "ib");
81 break;
82 }
83 printReg(ss, base);
84 if (wb) {
85 ss << "!";
86 }
87 return ss.str();
88}
89
65void
66Memory::printInst(std::ostream &os, AddrMode addrMode) const
67{
68 printMnemonic(os);
69 printDest(os);
70 os << ", [";
71 printReg(os, base);
72 if (addrMode != AddrMd_PostIndex) {

--- 14 unchanged lines hidden --- 		90void
91Memory::printInst(std::ostream &os, AddrMode addrMode) const
92{
93 printMnemonic(os);
94 printDest(os);
95 os << ", [";
96 printReg(os, base);
97 if (addrMode != AddrMd_PostIndex) {

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