mem.cc (7132:83b433d6e600) mem.cc (7205:e3dfcdf19561)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 29 unchanged lines hidden (view full) ---

38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/mem.hh"
44#include "base/loader/symtab.hh"
45
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 29 unchanged lines hidden (view full) ---

38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/mem.hh"
44#include "base/loader/symtab.hh"
45
46using namespace std;
47
46namespace ArmISA
47{
48
48namespace ArmISA
49{
50
51string
52Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
53{
54 stringstream ss;
55 printMnemonic(ss);
56 printReg(ss, dest);
57 ss << ", ";
58 printReg(ss, op1);
59 ss << ", [";
60 printReg(ss, base);
61 ss << "]";
62 return ss.str();
63}
64
49void
50Memory::printInst(std::ostream &os, AddrMode addrMode) const
51{
52 printMnemonic(os);
53 printReg(os, dest);
54 os << ", [";
55 printReg(os, base);
56 if (addrMode != AddrMd_PostIndex) {

--- 14 unchanged lines hidden --- 		65void
66Memory::printInst(std::ostream &os, AddrMode addrMode) const
67{
68 printMnemonic(os);
69 printReg(os, dest);
70 os << ", [";
71 printReg(os, base);
72 if (addrMode != AddrMd_PostIndex) {

--- 14 unchanged lines hidden ---