mem.cc (6307:067515d22824) | mem.cc (7118:444a3e126366) |
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1/* Copyright (c) 2007-2008 The Florida State University | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University |
2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the --- 17 unchanged lines hidden (view full) --- 27 * Authors: Stephen Hines 28 */ 29 30#include "arch/arm/insts/mem.hh" 31#include "base/loader/symtab.hh" 32 33namespace ArmISA 34{ | 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the --- 17 unchanged lines hidden (view full) --- 40 * Authors: Stephen Hines 41 */ 42 43#include "arch/arm/insts/mem.hh" 44#include "base/loader/symtab.hh" 45 46namespace ArmISA 47{ |
48 49void 50MemoryNew::printInst(std::ostream &os, AddrMode addrMode) const 51{ 52 printMnemonic(os); 53 printReg(os, dest); 54 os << ", ["; 55 printReg(os, base); 56 if (addrMode != AddrMd_PostIndex) { 57 os << ", "; 58 printOffset(os); 59 os << "]"; 60 if (addrMode == AddrMd_PreIndex) { 61 os << "!"; 62 } 63 } else { 64 os << "] "; 65 printOffset(os); 66 67 } 68} 69 |
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35std::string 36Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 37{ 38 std::stringstream ss; 39 printMnemonic(ss); 40 printReg(ss, machInst.rd); 41 ss << ", ["; 42 printReg(ss, machInst.rn); 43 ss << ", "; 44 if (machInst.puswl.prepost == 1) 45 printOffset(ss); 46 ss << "]"; 47 if (machInst.puswl.prepost == 0) 48 printOffset(ss); 49 else if (machInst.puswl.writeback) 50 ss << "!"; 51 return ss.str(); 52} | 70std::string 71Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 72{ 73 std::stringstream ss; 74 printMnemonic(ss); 75 printReg(ss, machInst.rd); 76 ss << ", ["; 77 printReg(ss, machInst.rn); 78 ss << ", "; 79 if (machInst.puswl.prepost == 1) 80 printOffset(ss); 81 ss << "]"; 82 if (machInst.puswl.prepost == 0) 83 printOffset(ss); 84 else if (machInst.puswl.writeback) 85 ss << "!"; 86 return ss.str(); 87} |
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53} | 89} |