1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43#include "arch/arm/insts/mem.hh" 44#include "base/loader/symtab.hh" 45 46using namespace std; 47 48namespace ArmISA 49{ 50 |
51void 52MemoryReg::printOffset(std::ostream &os) const 53{ 54 if (!add) 55 os << "-"; 56 printReg(os, index); 57 if (shiftType != LSL || shiftAmt != 0) { 58 switch (shiftType) { 59 case LSL: 60 ccprintf(os, " LSL #%d", shiftAmt); 61 break; 62 case LSR: 63 if (shiftAmt == 0) { 64 ccprintf(os, " LSR #%d", 32); 65 } else { 66 ccprintf(os, " LSR #%d", shiftAmt); 67 } 68 break; 69 case ASR: 70 if (shiftAmt == 0) { 71 ccprintf(os, " ASR #%d", 32); 72 } else { 73 ccprintf(os, " ASR #%d", shiftAmt); 74 } 75 break; 76 case ROR: 77 if (shiftAmt == 0) { 78 ccprintf(os, " RRX"); 79 } else { 80 ccprintf(os, " ROR #%d", shiftAmt); 81 } 82 break; 83 } 84 } 85} 86 |
87string 88Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const 89{ 90 stringstream ss; 91 printMnemonic(ss); 92 printReg(ss, dest); 93 ss << ", "; 94 printReg(ss, op1); --- 108 unchanged lines hidden --- |