1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/mem.hh"
44#include "base/loader/symtab.hh"
45
46using namespace std;
47
48namespace ArmISA
49{
50
51void
52MemoryReg::printOffset(std::ostream &os) const
53{
54 if (!add)
55 os << "-";
56 printReg(os, index);
57 if (shiftType != LSL || shiftAmt != 0) {
58 switch (shiftType) {
59 case LSL:
60 ccprintf(os, " LSL #%d", shiftAmt);
61 break;
62 case LSR:
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/mem.hh"
44#include "base/loader/symtab.hh"
45
46using namespace std;
47
48namespace ArmISA
49{
50
51void
52MemoryReg::printOffset(std::ostream &os) const
53{
54 if (!add)
55 os << "-";
56 printReg(os, index);
57 if (shiftType != LSL || shiftAmt != 0) {
58 switch (shiftType) {
59 case LSL:
60 ccprintf(os, " LSL #%d", shiftAmt);
61 break;
62 case LSR:
|
63 if (shiftAmt == 0) {
64 ccprintf(os, " LSR #%d", 32);
65 } else {
66 ccprintf(os, " LSR #%d", shiftAmt);
67 }
| 63 ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
|
68 break;
69 case ASR:
| 64 break;
65 case ASR:
|
70 if (shiftAmt == 0) {
71 ccprintf(os, " ASR #%d", 32);
72 } else {
73 ccprintf(os, " ASR #%d", shiftAmt);
74 }
| 66 ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
|
75 break;
76 case ROR:
77 if (shiftAmt == 0) {
78 ccprintf(os, " RRX");
79 } else {
80 ccprintf(os, " ROR #%d", shiftAmt);
81 }
82 break;
83 }
84 }
85}
86
87string
88Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
89{
90 stringstream ss;
91 printMnemonic(ss);
92 printReg(ss, dest);
93 ss << ", ";
94 printReg(ss, op1);
95 ss << ", [";
96 printReg(ss, base);
97 ss << "]";
98 return ss.str();
99}
100
101string
102RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
103{
104 stringstream ss;
105 switch (mode) {
106 case DecrementAfter:
107 printMnemonic(ss, "da");
108 break;
109 case DecrementBefore:
110 printMnemonic(ss, "db");
111 break;
112 case IncrementAfter:
113 printMnemonic(ss, "ia");
114 break;
115 case IncrementBefore:
116 printMnemonic(ss, "ib");
117 break;
118 }
119 printReg(ss, base);
120 if (wb) {
121 ss << "!";
122 }
123 return ss.str();
124}
125
126string
127SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
128{
129 stringstream ss;
130 switch (mode) {
131 case DecrementAfter:
132 printMnemonic(ss, "da");
133 break;
134 case DecrementBefore:
135 printMnemonic(ss, "db");
136 break;
137 case IncrementAfter:
138 printMnemonic(ss, "ia");
139 break;
140 case IncrementBefore:
141 printMnemonic(ss, "ib");
142 break;
143 }
144 printReg(ss, INTREG_SP);
145 if (wb) {
146 ss << "!";
147 }
148 ss << ", #";
149 switch (regMode) {
150 case MODE_USER:
151 ss << "user";
152 break;
153 case MODE_FIQ:
154 ss << "fiq";
155 break;
156 case MODE_IRQ:
157 ss << "irq";
158 break;
159 case MODE_SVC:
160 ss << "supervisor";
161 break;
162 case MODE_MON:
163 ss << "monitor";
164 break;
165 case MODE_ABORT:
166 ss << "abort";
167 break;
168 case MODE_UNDEFINED:
169 ss << "undefined";
170 break;
171 case MODE_SYSTEM:
172 ss << "system";
173 break;
174 default:
175 ss << "unrecognized";
176 break;
177 }
178 return ss.str();
179}
180
181void
182Memory::printInst(std::ostream &os, AddrMode addrMode) const
183{
184 printMnemonic(os);
185 printDest(os);
186 os << ", [";
187 printReg(os, base);
188 if (addrMode != AddrMd_PostIndex) {
189 os << ", ";
190 printOffset(os);
191 os << "]";
192 if (addrMode == AddrMd_PreIndex) {
193 os << "!";
194 }
195 } else {
196 os << "] ";
197 printOffset(os);
198
199 }
200}
201
202}
| 67 break;
68 case ROR:
69 if (shiftAmt == 0) {
70 ccprintf(os, " RRX");
71 } else {
72 ccprintf(os, " ROR #%d", shiftAmt);
73 }
74 break;
75 }
76 }
77}
78
79string
80Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
81{
82 stringstream ss;
83 printMnemonic(ss);
84 printReg(ss, dest);
85 ss << ", ";
86 printReg(ss, op1);
87 ss << ", [";
88 printReg(ss, base);
89 ss << "]";
90 return ss.str();
91}
92
93string
94RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
95{
96 stringstream ss;
97 switch (mode) {
98 case DecrementAfter:
99 printMnemonic(ss, "da");
100 break;
101 case DecrementBefore:
102 printMnemonic(ss, "db");
103 break;
104 case IncrementAfter:
105 printMnemonic(ss, "ia");
106 break;
107 case IncrementBefore:
108 printMnemonic(ss, "ib");
109 break;
110 }
111 printReg(ss, base);
112 if (wb) {
113 ss << "!";
114 }
115 return ss.str();
116}
117
118string
119SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
120{
121 stringstream ss;
122 switch (mode) {
123 case DecrementAfter:
124 printMnemonic(ss, "da");
125 break;
126 case DecrementBefore:
127 printMnemonic(ss, "db");
128 break;
129 case IncrementAfter:
130 printMnemonic(ss, "ia");
131 break;
132 case IncrementBefore:
133 printMnemonic(ss, "ib");
134 break;
135 }
136 printReg(ss, INTREG_SP);
137 if (wb) {
138 ss << "!";
139 }
140 ss << ", #";
141 switch (regMode) {
142 case MODE_USER:
143 ss << "user";
144 break;
145 case MODE_FIQ:
146 ss << "fiq";
147 break;
148 case MODE_IRQ:
149 ss << "irq";
150 break;
151 case MODE_SVC:
152 ss << "supervisor";
153 break;
154 case MODE_MON:
155 ss << "monitor";
156 break;
157 case MODE_ABORT:
158 ss << "abort";
159 break;
160 case MODE_UNDEFINED:
161 ss << "undefined";
162 break;
163 case MODE_SYSTEM:
164 ss << "system";
165 break;
166 default:
167 ss << "unrecognized";
168 break;
169 }
170 return ss.str();
171}
172
173void
174Memory::printInst(std::ostream &os, AddrMode addrMode) const
175{
176 printMnemonic(os);
177 printDest(os);
178 os << ", [";
179 printReg(os, base);
180 if (addrMode != AddrMd_PostIndex) {
181 os << ", ";
182 printOffset(os);
183 os << "]";
184 if (addrMode == AddrMd_PreIndex) {
185 os << "!";
186 }
187 } else {
188 os << "] ";
189 printOffset(os);
190
191 }
192}
193
194}
|