1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38import m5.objects
39import inspect
40import sys
41from textwrap import TextWrapper
42
43# Dictionary of mapping names of real CPU models to classes.
44_cpu_classes = {}
45
46# CPU aliases. The CPUs listed here might not be compiled, we make
47# sure they exist before we add them to the CPU list. A target may be
48# specified as a tuple, in which case the first available CPU model in
49# the tuple will be used as the target.
50_cpu_aliases_all = [
51 ("timing", "TimingSimpleCPU"),
52 ("atomic", "AtomicSimpleCPU"),
53 ("minor", "MinorCPU"),
54 ("detailed", "DerivO3CPU"),
55 ("kvm", ("ArmKvmCPU", "ArmV8KvmCPU", "X86KvmCPU")),
56 ("trace", "TraceCPU"),
57 ]
58
59# Filtered list of aliases. Only aliases for existing CPUs exist in
60# this list.
61_cpu_aliases = {}
62
63
64def is_cpu_class(cls):
65 """Determine if a class is a CPU that can be instantiated"""
66
67 # We can't use the normal inspect.isclass because the ParamFactory
68 # and ProxyFactory classes have a tendency to confuse it.
69 try:
70 return issubclass(cls, m5.objects.BaseCPU) and \
71 not cls.abstract and \
72 not issubclass(cls, m5.objects.CheckerCPU)
| 1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38import m5.objects
39import inspect
40import sys
41from textwrap import TextWrapper
42
43# Dictionary of mapping names of real CPU models to classes.
44_cpu_classes = {}
45
46# CPU aliases. The CPUs listed here might not be compiled, we make
47# sure they exist before we add them to the CPU list. A target may be
48# specified as a tuple, in which case the first available CPU model in
49# the tuple will be used as the target.
50_cpu_aliases_all = [
51 ("timing", "TimingSimpleCPU"),
52 ("atomic", "AtomicSimpleCPU"),
53 ("minor", "MinorCPU"),
54 ("detailed", "DerivO3CPU"),
55 ("kvm", ("ArmKvmCPU", "ArmV8KvmCPU", "X86KvmCPU")),
56 ("trace", "TraceCPU"),
57 ]
58
59# Filtered list of aliases. Only aliases for existing CPUs exist in
60# this list.
61_cpu_aliases = {}
62
63
64def is_cpu_class(cls):
65 """Determine if a class is a CPU that can be instantiated"""
66
67 # We can't use the normal inspect.isclass because the ParamFactory
68 # and ProxyFactory classes have a tendency to confuse it.
69 try:
70 return issubclass(cls, m5.objects.BaseCPU) and \
71 not cls.abstract and \
72 not issubclass(cls, m5.objects.CheckerCPU)
|
74 return False
75
76def get(name):
77 """Get a CPU class from a user provided class name or alias."""
78
79 real_name = _cpu_aliases.get(name, name)
80
81 try:
82 cpu_class = _cpu_classes[real_name]
83 return cpu_class
84 except KeyError:
85 print "%s is not a valid CPU model." % (name,)
86 sys.exit(1)
87
88def print_cpu_list():
89 """Print a list of available CPU classes including their aliases."""
90
91 print "Available CPU classes:"
92 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
93 for name, cls in _cpu_classes.items():
94 print "\t%s" % name
95
96 # Try to extract the class documentation from the class help
97 # string.
98 doc = inspect.getdoc(cls)
99 if doc:
100 for line in doc_wrapper.wrap(doc):
101 print line
102
103 if _cpu_aliases:
104 print "\nCPU aliases:"
105 for alias, target in _cpu_aliases.items():
106 print "\t%s => %s" % (alias, target)
107
108def cpu_names():
109 """Return a list of valid CPU names."""
110 return _cpu_classes.keys() + _cpu_aliases.keys()
111
112def config_etrace(cpu_cls, cpu_list, options):
113 if issubclass(cpu_cls, m5.objects.DerivO3CPU):
114 # Assign the same file name to all cpus for now. This must be
115 # revisited when creating elastic traces for multi processor systems.
116 for cpu in cpu_list:
117 # Attach the elastic trace probe listener. Set the protobuf trace
118 # file names. Set the dependency window size equal to the cpu it
119 # is attached to.
120 cpu.traceListener = m5.objects.ElasticTrace(
121 instFetchTraceFile = options.inst_trace_file,
122 dataDepTraceFile = options.data_trace_file,
123 depWindowSize = 3 * cpu.numROBEntries)
124 # Make the number of entries in the ROB, LQ and SQ very
125 # large so that there are no stalls due to resource
126 # limitation as such stalls will get captured in the trace
127 # as compute delay. For replay, ROB, LQ and SQ sizes are
128 # modelled in the Trace CPU.
129 cpu.numROBEntries = 512;
130 cpu.LQEntries = 128;
131 cpu.SQEntries = 128;
132 else:
133 fatal("%s does not support data dependency tracing. Use a CPU model of"
134 " type or inherited from DerivO3CPU.", cpu_cls)
135
136# The ARM detailed CPU is special in the sense that it doesn't exist
137# in the normal object hierarchy, so we have to add it manually.
138try:
139 from O3_ARM_v7a import O3_ARM_v7a_3
140 _cpu_classes["arm_detailed"] = O3_ARM_v7a_3
141except:
142 pass
143
144# Add all CPUs in the object hierarchy.
145for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
146 _cpu_classes[name] = cls
147
148for alias, target in _cpu_aliases_all:
149 if isinstance(target, tuple):
150 # Some aliases contain a list of CPU model sorted in priority
151 # order. Use the first target that's available.
152 for t in target:
153 if t in _cpu_classes:
154 _cpu_aliases[alias] = t
155 break
156 elif target in _cpu_classes:
157 # Normal alias
158 _cpu_aliases[alias] = target
| 74 return False
75
76def get(name):
77 """Get a CPU class from a user provided class name or alias."""
78
79 real_name = _cpu_aliases.get(name, name)
80
81 try:
82 cpu_class = _cpu_classes[real_name]
83 return cpu_class
84 except KeyError:
85 print "%s is not a valid CPU model." % (name,)
86 sys.exit(1)
87
88def print_cpu_list():
89 """Print a list of available CPU classes including their aliases."""
90
91 print "Available CPU classes:"
92 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
93 for name, cls in _cpu_classes.items():
94 print "\t%s" % name
95
96 # Try to extract the class documentation from the class help
97 # string.
98 doc = inspect.getdoc(cls)
99 if doc:
100 for line in doc_wrapper.wrap(doc):
101 print line
102
103 if _cpu_aliases:
104 print "\nCPU aliases:"
105 for alias, target in _cpu_aliases.items():
106 print "\t%s => %s" % (alias, target)
107
108def cpu_names():
109 """Return a list of valid CPU names."""
110 return _cpu_classes.keys() + _cpu_aliases.keys()
111
112def config_etrace(cpu_cls, cpu_list, options):
113 if issubclass(cpu_cls, m5.objects.DerivO3CPU):
114 # Assign the same file name to all cpus for now. This must be
115 # revisited when creating elastic traces for multi processor systems.
116 for cpu in cpu_list:
117 # Attach the elastic trace probe listener. Set the protobuf trace
118 # file names. Set the dependency window size equal to the cpu it
119 # is attached to.
120 cpu.traceListener = m5.objects.ElasticTrace(
121 instFetchTraceFile = options.inst_trace_file,
122 dataDepTraceFile = options.data_trace_file,
123 depWindowSize = 3 * cpu.numROBEntries)
124 # Make the number of entries in the ROB, LQ and SQ very
125 # large so that there are no stalls due to resource
126 # limitation as such stalls will get captured in the trace
127 # as compute delay. For replay, ROB, LQ and SQ sizes are
128 # modelled in the Trace CPU.
129 cpu.numROBEntries = 512;
130 cpu.LQEntries = 128;
131 cpu.SQEntries = 128;
132 else:
133 fatal("%s does not support data dependency tracing. Use a CPU model of"
134 " type or inherited from DerivO3CPU.", cpu_cls)
135
136# The ARM detailed CPU is special in the sense that it doesn't exist
137# in the normal object hierarchy, so we have to add it manually.
138try:
139 from O3_ARM_v7a import O3_ARM_v7a_3
140 _cpu_classes["arm_detailed"] = O3_ARM_v7a_3
141except:
142 pass
143
144# Add all CPUs in the object hierarchy.
145for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
146 _cpu_classes[name] = cls
147
148for alias, target in _cpu_aliases_all:
149 if isinstance(target, tuple):
150 # Some aliases contain a list of CPU model sorted in priority
151 # order. Use the first target that's available.
152 for t in target:
153 if t in _cpu_classes:
154 _cpu_aliases[alias] = t
155 break
156 elif target in _cpu_classes:
157 # Normal alias
158 _cpu_aliases[alias] = target
|