| /gem5/src/cpu/minor/ |
| H A D | scoreboard.hh | 68 const unsigned numRegs; member in class:Minor::Scoreboard
96 numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
100 numResults(numRegs, 0),
101 numUnpredictableResults(numRegs, 0),
102 fuIndices(numRegs, 0),
103 returnCycle(numRegs, Cycles(0)),
104 writingInst(numRegs, 0)
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| H A D | scoreboard.cc | 297 while (i < numRegs) {
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| /gem5/src/dev/x86/ |
| H A D | cmos.cc | 88 assert(reg < numRegs);
105 assert(reg < numRegs);
127 SERIALIZE_ARRAY(regs, numRegs);
137 UNSERIALIZE_ARRAY(regs, numRegs);
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| H A D | cmos.hh | 49 static const int numRegs = 128; member in class:X86ISA::Cmos
51 uint8_t regs[numRegs];
81 memset(regs, 0, numRegs * sizeof(uint8_t));
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| /gem5/src/gpu-compute/ |
| H A D | condition_register_state.hh | 89 int numRegs() { return c_reg.size(); } function in class:ConditionRegisterState
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| H A D | vector_register_file.cc | 82 status = status | (nxtBusy.at((idx + 1) % numRegs()));
94 status = status | (busy.at((idx + 1) % numRegs()));
106 nxtBusy.at((regIdx + 1) % numRegs()) = value;
116 busy.at((regIdx + 1) % numRegs()) = value;
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| H A D | vector_register_file.hh | 94 int numRegs() const { return numRegsPerSimd; } function in class:VrfAccessType::VectorRegisterFile
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| H A D | wavefront.cc | 299 return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs();
908 for (int i = 0; i < condRegState->numRegs(); i++) {
967 for (int i = 0; i < condRegState->numRegs(); i++) {
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| H A D | compute_unit.cc | 159 numVecRegsPerSimd = vrf[0]->numRegs();
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| /gem5/src/arch/arm/insts/ |
| H A D | macromem.hh | 166 uint8_t eSize, dataSize, numStructElems, numRegs, step; member in class:ArmISA::MicroNeonMixOp64
174 numRegs(_numRegs), step(_step)
204 uint8_t eSize, dataSize, numStructElems, numRegs; member in class:ArmISA::VldMultOp64
209 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
216 uint8_t eSize, dataSize, numStructElems, numRegs; member in class:ArmISA::VstMultOp64
221 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
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| H A D | macromem.cc | 1123 uint8_t numStructElems, uint8_t numRegs, bool wb) :
1132 int totNumBytes = numRegs * dataSize / 8;
1143 int numMarshalMicroops = numRegs / 2 + (numRegs % 2 ? 1 : 0);
1175 switch(numRegs) {
1208 uint8_t numStructElems, uint8_t numRegs, bool wb) :
1217 int totNumBytes = numRegs * dataSize / 8;
1235 switch (numRegs) {
1120 VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb) argument
1205 VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb) argument
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| /gem5/src/arch/hsail/insts/ |
| H A D | main.cc | 169 w->computeUnit->vrf[w->simdId]->numRegs();
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| /gem5/src/arch/hsail/ |
| H A D | operand.hh | 327 assert(regIdx < w->condRegState->numRegs());
340 assert(regIdx < w->condRegState->numRegs());
|