1/*
2 * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Authors: John Kalamatianos,
34 *          Mark Wyse
35 */
36
37#ifndef __VECTOR_REGISTER_FILE_HH__
38#define __VECTOR_REGISTER_FILE_HH__
39
40#include <list>
41
42#include "base/statistics.hh"
43#include "base/trace.hh"
44#include "base/types.hh"
45#include "debug/GPUVRF.hh"
46#include "gpu-compute/vector_register_state.hh"
47#include "sim/sim_object.hh"
48
49class ComputeUnit;
50class Shader;
51class SimplePoolManager;
52class Wavefront;
53
54struct VectorRegisterFileParams;
55
56enum class VrfAccessType : uint8_t
57{
58    READ = 0x01,
59    WRITE = 0x02,
60    RD_WR = READ | WRITE
61};
62
63// Vector Register File
64class VectorRegisterFile : public SimObject
65{
66  public:
67    VectorRegisterFile(const VectorRegisterFileParams *p);
68
69    void setParent(ComputeUnit *_computeUnit);
70
71    // Read a register
72    template<typename T>
73    T
74    read(int regIdx, int threadId=0)
75    {
76        T p0 = vgprState->read<T>(regIdx, threadId);
77        DPRINTF(GPUVRF, "reading vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)p0);
78
79        return p0;
80    }
81
82    // Write a register
83    template<typename T>
84    void
85    write(int regIdx, T value, int threadId=0)
86    {
87        DPRINTF(GPUVRF, "writing vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)value);
88        vgprState->write<T>(regIdx, value, threadId);
89    }
90
91    uint8_t regBusy(int idx, uint32_t operandSize) const;
92    uint8_t regNxtBusy(int idx, uint32_t operandSize) const;
93
94    int numRegs() const { return numRegsPerSimd; }
95
96    void markReg(int regIdx, uint32_t operandSize, uint8_t value);
97    void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value);
98
99    virtual void exec(GPUDynInstPtr ii, Wavefront *w);
100
101    virtual int exec(uint64_t dynamic_id, Wavefront *w,
102                     std::vector<uint32_t> &regVec, uint32_t operandSize,
103                     uint64_t timestamp);
104
105    bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const;
106    virtual void updateEvents() { }
107    virtual void updateResources(Wavefront *w, GPUDynInstPtr ii);
108
109    virtual bool
110    isReadConflict(int memWfId, int exeWfId) const
111    {
112        return false;
113    }
114
115    virtual bool
116    isWriteConflict(int memWfId, int exeWfId) const
117    {
118        return false;
119    }
120
121    virtual bool vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w,
122                                       GPUDynInstPtr ii,
123                                       VrfAccessType accessType);
124
125    virtual bool vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii,
126                                       VrfAccessType accessType);
127
128    SimplePoolManager *manager;
129
130  protected:
131    ComputeUnit* computeUnit;
132    int simdId;
133
134    // flag indicating if a register is busy
135    std::vector<uint8_t> busy;
136    // flag indicating if a register will be busy (by instructions
137    // in the SIMD pipeline)
138    std::vector<uint8_t> nxtBusy;
139
140    // numer of registers (bank size) per simd unit (bank)
141    int numRegsPerSimd;
142
143    // vector register state
144    VecRegisterState *vgprState;
145};
146
147#endif // __VECTOR_REGISTER_FILE_HH__
148