Searched refs:load_inst (Results 1 - 5 of 5) sorted by relevance
/gem5/src/cpu/o3/ |
H A D | lsq_unit.hh | 248 void insertLoad(const DynInstPtr &load_inst); 616 const DynInstPtr& load_inst = load_req.instruction(); local 619 assert(load_inst); 621 assert(!load_inst->isExecuted()); 629 (load_idx != loadQueue.head() || !load_inst->isAtCommit())) { 632 iewStage->rescheduleMemInst(load_inst); 633 load_inst->clearIssued(); 634 load_inst->effAddrValid(false); 637 load_inst->seqNum, load_inst [all...] |
H A D | lsq_unit_impl.hh | 293 LSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst) argument 299 load_inst->pcState(), loadQueue.tail(), load_inst->seqNum); 304 load_inst->sqIt = storeQueue.end(); 307 loadQueue.back().set(load_inst); 308 load_inst->lqIdx = loadQueue.tail(); 309 load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx);
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H A D | lsq_impl.hh | 232 LSQ<Impl>::insertLoad(const DynInstPtr &load_inst) 234 ThreadID tid = load_inst->threadNumber; 236 thread[tid].insertLoad(load_inst);
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H A D | lsq.hh | 845 void insertLoad(const DynInstPtr &load_inst);
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/gem5/tests/test-progs/asmtest/src/riscv/isa/macros/scalar/ |
H A D | test_macros.h | 224 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ 229 load_inst x30, offset(x1); \ 259 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ 268 load_inst x30, offset(x2); \ 275 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ 284 load_inst x30, offset(x2); \
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