Lines Matching refs:load_inst
248 void insertLoad(const DynInstPtr &load_inst);
616 const DynInstPtr& load_inst = load_req.instruction();
619 assert(load_inst);
621 assert(!load_inst->isExecuted());
629 (load_idx != loadQueue.head() || !load_inst->isAtCommit())) {
632 iewStage->rescheduleMemInst(load_inst);
633 load_inst->clearIssued();
634 load_inst->effAddrValid(false);
637 load_inst->seqNum, load_inst->pcState());
646 load_inst->seqNum, load_inst->pcState());
651 load_idx - 1, load_inst->sqIt._idx, storeQueue.head() - 1,
658 load_inst->recordResult(false);
659 TheISA::handleLockedRead(load_inst.get(), req->mainRequest());
660 load_inst->recordResult(true);
664 assert(!load_inst->memData);
665 load_inst->memData = new uint8_t[MaxDataBytes];
670 main_pkt->dataStatic(load_inst->memData);
674 WritebackEvent *wb = new WritebackEvent(load_inst, main_pkt, this);
680 auto store_it = load_inst->sqIt;
687 assert(store_it->instruction()->seqNum < load_inst->seqNum);
723 if (!load_inst->memData) {
724 load_inst->memData =
728 memset(load_inst->memData, 0,
731 memcpy(load_inst->memData,
741 data_pkt->dataStatic(load_inst->memData);
752 WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt,
793 load_inst->seqNum <
802 iewStage->rescheduleMemInst(load_inst);
803 load_inst->clearIssued();
804 load_inst->effAddrValid(false);
823 load_inst->seqNum, load_inst->pcState());
826 if (!load_inst->memData) {
827 load_inst->memData = new uint8_t[req->mainRequest()->getSize()];
841 state->inst = load_inst;
848 iewStage->blockMemInst(load_inst);