Searched hist:11751 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/mem/cache/
H A Dmshr.cc11751:cd6248b276a8 Mon Dec 05 16:48:00 EST 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Respond to InvalidateReq when the block is (pending) dirty

Previously when an InvalidateReq snooped a cache with a dirty block or
a pending modified MSHR, it would invalidate the block or set the
postInv flag. The cache would not send an InvalidateResp. though,
causing memory order violations. This patches changes this behavior,
making the cache with the dirty block or pending modified MSHR the
ordering point.

Change-Id: Ib4c31012f4f6693ffb137cd77258b160fbc239ca
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
H A Dcache.cc11751:cd6248b276a8 Mon Dec 05 16:48:00 EST 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Respond to InvalidateReq when the block is (pending) dirty

Previously when an InvalidateReq snooped a cache with a dirty block or
a pending modified MSHR, it would invalidate the block or set the
postInv flag. The cache would not send an InvalidateResp. though,
causing memory order violations. This patches changes this behavior,
making the cache with the dirty block or pending modified MSHR the
ordering point.

Change-Id: Ib4c31012f4f6693ffb137cd77258b160fbc239ca
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>

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