Searched refs:writes (Results 1 - 9 of 9) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.cc3113 .allPrivileges().exceptUserMode().writes(0);
3115 .allPrivileges().exceptUserMode().writes(0);
3117 .allPrivileges().exceptUserMode().writes(0);
3119 .allPrivileges().exceptUserMode().writes(0);
3121 .allPrivileges().exceptUserMode().writes(0);
3125 .allPrivileges().exceptUserMode().writes(0);
3127 .allPrivileges().exceptUserMode().writes(0);
3129 .allPrivileges().exceptUserMode().writes(0);
3131 .allPrivileges().exceptUserMode().writes(0);
3133 .allPrivileges().exceptUserMode().writes(
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H A Disa.hh130 // raz/rao implies writes ignored
346 chain writes(bool v) const { function in class:ArmISA::ISA::MiscRegLUTEntryInitializer
/gem5/src/mem/
H A Dmem_checker.cc68 writes.insert(std::make_pair(serial,
75 auto it = writes.find(serial);
77 if (it == writes.end()) {
93 // All writes have completed, this cluster is now complete and will be
94 // assigned the max of completion tick values among all writes.
98 // until all writes have completed.
106 if (!writes.erase(serial)) {
111 if (--numIncomplete == 0 && !writes.empty()) {
142 // preceding & overlapping writes.
145 for (const auto& addr_write : cluster->writes) {
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H A Dmem_checker.hh59 * MemChecker. Verifies that reads observe the values from permissible writes.
63 * there is overlap between writes, they could be reordered by the memory
69 * reads or writes. This precludes us from discovering single-copy atomicity
124 * for writes, the value written upon start; for reads, the value read
137 * The WriteCluster class captures sets of writes where all writes are
138 * overlapping with at least one other write. Capturing writes in this way
139 * simplifies pruning of writes.
185 * Map of Serial --> Transaction of all writes in cluster; contains
188 std::unordered_map<Serial, Transaction> writes; member in class:MemChecker::WriteCluster
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Dbreakpoint.S63 # Make sure writes don't trap.
/gem5/ext/mcpat/
H A Dmemoryctrl.cc86 rtp_stats.writeAc.access = mcs.writes;
216 rtp_stats.writeAc.access = mcs.writes;
382 frontendBuffer->rtp_stats.writeAc.access = mcs.writes * mcp.llcBlockSize *
467 writeBuffer->rtp_stats.writeAc.access = mcs.writes * mcp.llcBlockSize *
475 "Arbitration Logic", (mcs.reads + mcs.writes),
576 ASSIGN_INT_IF("memory_writes", mcs.writes);
H A Dbasic_components.h459 double writes; member in class:MCStatistics
/gem5/src/arch/x86/
H A Dpagetable_walker.cc266 // On a functional access (page table lookup), writes should
626 writes.push_back(write);
632 if (inflight == 0 && read == NULL && writes.size() == 0) {
678 //Send off as many of the writes as we can.
679 while (writes.size()) {
680 PacketPtr write = writes.back();
681 writes.pop_back();
685 writes.push_back(write);
H A Dpagetable_walker.hh106 std::vector<PacketPtr> writes; member in class:X86ISA::Walker::WalkerState

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