Searched refs:tr (Results 1 - 10 of 10) sorted by relevance
/gem5/src/dev/arm/ |
H A D | smmu_v3_transl.cc | 169 TranslResult tr; local 176 if (hazard4kCheck() || ifcTLBLookup(yield, tr, wasPrefetched)) 181 tr = smmuTranslation(yield); 183 if (tr.fault == FAULT_NONE) 184 ifcTLBUpdate(yield, tr); 192 if (!microTLBLookup(yield, tr)) { 193 bool hit = ifcTLBLookup(yield, tr, wasPrefetched); 197 hit = ifcTLBLookup(yield, tr, wasPrefetched); 210 tr = smmuTranslation(yield); 212 if (tr 238 TranslResult tr; local 250 TranslResult tr; local 310 microTLBLookup(Yield &yield, TranslResult &tr) argument 341 ifcTLBLookup(Yield &yield, TranslResult &tr, bool &wasPrefetched) argument 376 smmuTLBLookup(Yield &yield, TranslResult &tr) argument 407 microTLBUpdate(Yield &yield, const TranslResult &tr) argument 439 ifcTLBUpdate(Yield &yield, const TranslResult &tr) argument 476 smmuTLBUpdate(Yield &yield, const TranslResult &tr) argument 577 findConfig(Yield &yield, TranslContext &tc, TranslResult &tr) argument 760 TranslResult tr; local 770 TranslResult tr; local 792 TranslResult tr; local 844 TranslResult tr; local 854 TranslResult tr; local 869 TranslResult tr; local 903 TranslResult tr; local 949 TranslResult tr; local 985 TranslResult tr; local 1032 TranslResult tr; local [all...] |
H A D | smmu_v3_transl.hh | 108 bool microTLBLookup(Yield &yield, TranslResult &tr); 109 bool ifcTLBLookup(Yield &yield, TranslResult &tr, bool &wasPrefetched); 110 bool smmuTLBLookup(Yield &yield, TranslResult &tr); 112 void microTLBUpdate(Yield &yield, const TranslResult &tr); 113 void ifcTLBUpdate(Yield &yield, const TranslResult &tr); 114 void smmuTLBUpdate(Yield &yield, const TranslResult &tr); 118 bool findConfig(Yield &yield, TranslContext &tc, TranslResult &tr); 163 void completeTransaction(Yield &yield, const TranslResult &tr);
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_time.cpp | 214 value_type tr = SCAST<sc_dt::int64>( time_params->time_resolution ); local 216 while( ( tr % 10 ) == 0 ) { 217 tr /= 10; 220 assert( tr == 1 );
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/gem5/src/arch/sparc/ |
H A D | tlb.cc | 102 // TlbRange tr; 107 /* tr.va = va; 108 tr.size = PTE.size() - 1; 109 tr.contextId = context_id; 110 tr.partitionId = partition_id; 111 tr.real = real; 202 TlbRange tr; local 208 tr.va = va; 209 tr.size = 1; 210 tr 258 TlbRange tr; local [all...] |
/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.hh | 101 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
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/gem5/src/mem/ruby/structures/ |
H A D | CacheMemory.hh | 105 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
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H A D | CacheMemory.cc | 394 CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 416 tr->addRecord(cntrl, m_cache[i][j]->m_Address,
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/gem5/src/base/ |
H A D | inet.hh | 354 void tr(ip_opt_data_tr &tr) const;
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/gem5/ext/dnet/ |
H A D | ip.h | 344 struct ip_opt_data_tr tr; /* IP_OPT_TR */ member in union:ip_opt::ip_opt_data
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/gem5/src/cpu/kvm/ |
H A D | x86_cpu.cc | 153 APPLY_SEGMENT(tr, MISCREG_TR - MISCREG_SEG_SEL_BASE); \ 785 if (sregs.tr.type == SEG_SYS_TYPE_TSS_AVAILABLE) { 786 hack("tr.type (%i) is not busy. Forcing the busy bit.\n", 787 sregs.tr.type); 788 sregs.tr.type = SEG_SYS_TYPE_TSS_BUSY;
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