Searched refs:stage (Results 1 - 10 of 10) sorted by relevance

/gem5/src/mem/ruby/network/garnet2.0/
H A DVirtualChannel.cc71 VirtualChannel::need_stage(flit_stage stage, Cycles time) argument
76 return(t_flit->is_stage(stage, time));
H A DInputUnit.hh116 need_stage(int vc, flit_stage stage, Cycles time) argument
118 return m_vcs[vc]->need_stage(stage, time);
H A Dflit.hh76 is_stage(flit_stage stage, Cycles time) argument
78 return (stage == m_stage.first &&
H A DVirtualChannel.hh48 bool need_stage(flit_stage stage, Cycles time);
/gem5/src/gpu-compute/
H A Dexec_stage.cc66 ExecStage::collectStatistics(enum STAT_STATUS stage, int unitId) { argument
67 if (stage == IdleExec) {
87 } else if (stage == BusyExec) {
94 } else if (stage == PostExec) {
H A Dexec_stage.hh63 // Execution stage.
66 // The schedule stage is responsible for
95 void collectStatistics(enum STAT_STATUS stage, int unitId);
112 // and exec stage
/gem5/src/dev/arm/
H A Dsmmu_v3_transl.hh123 unsigned stage, unsigned level);
126 unsigned stage, unsigned level,
174 unsigned stage, unsigned level);
H A Dsmmu_v3_caches.cc1016 unsigned stage, unsigned level,
1021 Set &set = sets[pickSetIdx(va, vaMask, stage, level)];
1027 e.asid==asid && e.vmid==vmid && e.stage==stage && e.level==level)
1045 lookupsByStageLevel[stage-1][level]++;
1046 totalLookupsByStageLevel[stage-1][level]++;
1048 missesByStageLevel[stage-1][level]++;
1049 totalMissesByStageLevel[stage-1][level]++;
1062 assert(incoming.stage==1 || incoming.stage
1014 lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats) argument
1164 pickSetIdx(Addr va, Addr vaMask, unsigned stage, unsigned level) const argument
1192 pickEntryIdxToReplace(const Set &set, unsigned stage, unsigned level) argument
[all...]
H A Dsmmu_v3_caches.hh296 unsigned stage; member in struct:WalkCache::Entry
310 unsigned stage, unsigned level, bool updStats=true);
348 unsigned stage, unsigned level) const;
351 unsigned stage, unsigned level);
H A Dsmmu_v3_transl.cc610 // Establish stage 2 context first since
625 // Now fetch stage 1 config.
651 unsigned stage, unsigned level)
653 const char *indent = stage==2 ? " " : "";
657 stage == 1 ?
663 (stage == 1 ? smmu.walkCacheS1Levels : smmu.walkCacheS2Levels) :
671 asid, vmid, stage, level);
676 indent, addr, asid, vmid, walkEntry->pa, stage, level);
680 indent, addr, asid, vmid, stage, level);
690 unsigned stage, unsigne
647 walkCacheLookup( Yield &yield, const WalkCache::Entry *&walkEntry, Addr addr, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level) argument
688 walkCacheUpdate(Yield &yield, Addr va, Addr vaMask, Addr pa, unsigned stage, unsigned level, bool leaf, uint8_t permissions) argument
[all...]

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