Searched refs:ri (Results 1 - 6 of 6) sorted by relevance
/gem5/src/arch/arm/kvm/ |
H A D | armv8_cpu.cc | 141 for (const auto &ri : miscRegIdMap) { 142 const uint64_t value(tc->readMiscReg(ri.idx)); 143 DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value); 144 setOneReg(ri.kvm, value); 159 for (const auto &ri : intRegMap) 160 inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm)); 164 for (const auto &ri : miscRegMap) 165 inform(" %s: %s\n", ri.name, getAndFormatOneReg(ri [all...] |
H A D | arm_cpu.cc | 468 for (const KvmIntRegInfo *ri(kvmIntRegs); 469 ri->idx != NUM_INTREGS; ++ri) { 471 uint32_t value(getOneRegU32(ri->id)); 472 inform("%s: 0x%x\n", ri->name, value); 475 for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs); 476 ri->idx != NUM_MISCREGS; ++ri) { 478 uint32_t value(getOneRegU32(ri->id)); 479 inform("%s: 0x%x\n", miscRegName[ri [all...] |
/gem5/src/sim/ |
H A D | sim_object.cc | 137 SimObjectList::reverse_iterator ri = simObjectList.rbegin(); local 140 for (; ri != rend; ++ri) { 141 SimObject *obj = *ri;
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/gem5/configs/learning_gem5/part3/ |
H A D | msi_caches.py | 250 for ri in self.routers: 252 if ri == rj: continue # Don't connect a router to itself! 255 src_node = ri,
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H A D | ruby_caches_MI_example.py | 236 for ri in self.routers: 238 if ri == rj: continue # Don't connect a router to itself! 241 src_node = ri,
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/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_vector_datatype/ |
H A D | std_ulogic_vector_datatype.cpp | 427 std_ulogic_vector<4> ri; local 447 ri = ( rdata4.range(0,1), rdata4.range(2,3) ); 479 << ri[0] << "\t" << ri[1] << "\t" << ri[2] << "\t" << ri[3]
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