Searched refs:regNum (Results 1 - 7 of 7) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.hh57 * corresponding misc reg in regNum. The value of regNum is undefined
60 * @param regNum misc reg index (out).
64 bool msrAddrToIndex(MiscRegIndex &regNum, Addr addr);
H A Dmsr.cc149 msrAddrToIndex(MiscRegIndex &regNum, Addr addr) argument
155 regNum = it->second;
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc288 Addr regNum = 0; local
292 regNum = MISCREG_TSC;
295 regNum = MISCREG_APIC_BASE;
298 regNum = MISCREG_MTRRCAP;
301 regNum = MISCREG_SYSENTER_CS;
304 regNum = MISCREG_SYSENTER_ESP;
307 regNum = MISCREG_SYSENTER_EIP;
310 regNum = MISCREG_MCG_CAP;
313 regNum = MISCREG_MCG_STATUS;
316 regNum
[all...]
/gem5/src/arch/x86/
H A Dinterrupts.cc84 ApicRegIndex regNum; local
89 regNum = APIC_ID;
92 regNum = APIC_VERSION;
95 regNum = APIC_TASK_PRIORITY;
98 regNum = APIC_ARBITRATION_PRIORITY;
101 regNum = APIC_PROCESSOR_PRIORITY;
104 regNum = APIC_EOI;
107 regNum = APIC_LOGICAL_DESTINATION;
110 regNum = APIC_DESTINATION_FORMAT;
113 regNum
[all...]
H A Dtlb.cc184 MiscRegIndex regNum; local
185 if (!msrAddrToIndex(regNum, vaddr))
191 req->setPaddr((Addr)regNum * sizeof(RegVal));
/gem5/src/arch/hsail/
H A Doperand.cc52 regIdx = brigRegOp->regNum;
54 DPRINTF(GPUReg, "Operand: regNum: %d, kind: %d\n", regIdx,
165 regIdx = brigRegOp->regNum;
167 DPRINTF(GPUReg, "Operand: regNum: %d, kind: %d \n", regIdx,
H A DBrig_new.hpp1533 uint16_t regNum; member in struct:BrigOperandRegister

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