/gem5/src/gpu-compute/ |
H A D | vector_register_file.hh | 74 read(int regIdx, int threadId=0) argument 76 T p0 = vgprState->read<T>(regIdx, threadId); 77 DPRINTF(GPUVRF, "reading vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)p0); 85 write(int regIdx, T value, int threadId=0) argument 87 DPRINTF(GPUVRF, "writing vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)value); 88 vgprState->write<T>(regIdx, value, threadId); 96 void markReg(int regIdx, uint32_t operandSize, uint8_t value); 97 void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value);
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H A D | vector_register_state.hh | 63 read(int regIdx, int threadId=0) { argument 67 p0 = (T*)(&s_reg[regIdx][threadId]); 69 p0 = (T*)(&d_reg[regIdx][threadId]); 77 write(unsigned int regIdx, T value, int threadId=0) { argument 81 p0 = (T*)(&s_reg[regIdx][threadId]); 83 p0 = (T*)(&d_reg[regIdx][threadId]);
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H A D | condition_register_state.hh | 61 read(int regIdx, int threadId) argument 63 bool tmp = c_reg[regIdx][threadId]; 71 write(int regIdx, int threadId, T value) argument 73 c_reg[regIdx][threadId] = (bool)(value & 0x01); 77 markReg(int regIdx, uint8_t value) argument 79 busy.at(regIdx) = value;
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H A D | vector_register_file.cc | 101 VectorRegisterFile::preMarkReg(int regIdx, uint32_t operandSize, uint8_t value) argument 103 nxtBusy.at(regIdx) = value; 106 nxtBusy.at((regIdx + 1) % numRegs()) = value; 111 VectorRegisterFile::markReg(int regIdx, uint32_t operandSize, uint8_t value) argument 113 busy.at(regIdx) = value; 116 busy.at((regIdx + 1) % numRegs()) = value;
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H A D | compute_unit.hh | 223 uint32_t regIdx, 227 regIdxVec.push_back(std::make_pair(simdId, regIdx)); 232 ((regIdx + 1) % 222 registerEvent(uint32_t simdId, uint32_t regIdx, uint32_t operandSize, uint64_t when, uint8_t newStatus) argument
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/gem5/src/cpu/ |
H A D | reg_class.hh | 83 RegIndex regIdx; member in class:RegId 97 : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx), 109 return regClass == that.classValue() && regIdx == that.index() 123 regIdx < that.index() || 124 (regIdx == that.index() && elemIdx < that.elemIndex()))); 143 return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) || 145 regIdx == TheISA::ZeroReg)); 179 const RegIndex& index() const { return regIdx; } 180 RegIndex& index() { return regIdx; } 194 return regIdx; [all...] |
/gem5/src/arch/hsail/ |
H A D | operand.hh | 106 unsigned regIdx; member in class:BaseRegOperand 117 unsigned int regIndex() { return regIdx; } 159 assert(regIdx < w->maxSpVgprs); 166 vgprIdx = w->remap(regIdx, 1, 1); 171 vgprIdx = w->remap(regIdx, 2, 1); 176 vgprIdx = w->remap(regIdx,sizeof(OperandType), 1); 205 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val); 208 assert(regIdx < w->maxSpVgprs); 209 uint32_t vgprIdx = w->remap(regIdx, sizeof(OperandType), 1); 218 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, va [all...] |
H A D | operand.cc | 52 regIdx = brigRegOp->regNum; 54 DPRINTF(GPUReg, "Operand: regNum: %d, kind: %d\n", regIdx, 57 maxRegIdx = std::max(maxRegIdx, regIdx); 165 regIdx = brigRegOp->regNum; 167 DPRINTF(GPUReg, "Operand: regNum: %d, kind: %d \n", regIdx, 170 maxRegIdx = std::max(maxRegIdx, regIdx); 181 regIdx = strtoul(name + 2, &endptr, 10); 187 maxRegIdx = std::max(maxRegIdx, regIdx); 197 return csprintf("$s%d", regIdx); 203 return csprintf("$d%d", regIdx); [all...] |
/gem5/src/arch/arm/ |
H A D | utility.cc | 700 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, argument 714 regIdx = MISCREG_SPSR_FIQ; 718 regIdx = MISCREG_SPSR_IRQ; 722 regIdx = MISCREG_SPSR_SVC; 726 regIdx = MISCREG_SPSR_ABT; 730 regIdx = MISCREG_SPSR_UND; 734 regIdx = MISCREG_SPSR_MON; 738 regIdx = MISCREG_SPSR_HYP; 750 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8); 753 regIdx [all...] |
H A D | utility.hh | 354 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, 363 int regIdx; local 367 validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false); 368 return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
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