Searched refs:prefetch (Results 1 - 6 of 6) sorted by relevance

/gem5/src/gpu-compute/
H A Dtlb_coalescer.cc131 if (!incoming_state->prefetch)
174 if (!sender_state->prefetch)
245 bool update_stats = !sender_state->prefetch;
341 bool update_stats = !sender_state->prefetch;
465 bool update_stats = !tmp_sender_state->prefetch;
H A Dgpu_tlb.hh343 // Is this a TLB prefetch request?
344 bool prefetch; member in struct:X86ISA::GpuTLB::TranslationState
361 prefetch(_prefetch), issueTime(0),
H A Dgpu_tlb.cc1044 bool update_stats = !sender_state->prefetch;
1256 bool update_stats = !tmp_sender_state->prefetch;
1455 * prefetch, then sometimes you can try to prefetch something that
1464 if (!sender_state->prefetch && sender_state->tlbEntry)
1486 bool update_stats = !sender_state->prefetch;
1515 // If no valid translation from a prefetch, then just return
1516 if (sender_state->prefetch && !pkt->req->hasPaddr())
1538 if (!sender_state->prefetch) {
1550 // If this was a prefetch, the
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/gem5/src/dev/arm/
H A Dsmmu_v3_transl.hh61 static SMMUTranslRequest prefetch(Addr addr, uint32_t sid, uint32_t ssid);
H A Dsmmu_v3_transl.cc66 SMMUTranslRequest::prefetch(Addr addr, uint32_t sid, uint32_t ssid) function in class:SMMUTranslRequest
173 // Abort prefetch if:
201 // Issue prefetch if:
1218 SMMUTranslRequest::prefetch(addr, request.sid, request.ssid));
/gem5/src/mem/cache/prefetch/
H A DPrefetcher.py65 cxx_header = "mem/cache/prefetch/base.hh"
113 cxx_header = 'mem/cache/prefetch/multi.hh'
121 cxx_header = "mem/cache/prefetch/queued.hh"
126 queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
130 tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access")
134 # prefetch requests
147 cxx_header = "mem/cache/prefetch/stride.hh"
170 cxx_header = "mem/cache/prefetch/tagged.hh"
177 cxx_header = "mem/cache/prefetch/indirect_memory.hh"
187 max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distanc
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