Searched refs:mvfr0 (Results 1 - 1 of 1) sorted by relevance

/gem5/src/arch/arm/
H A Disa.cc149 MVFR0 mvfr0 = 0; local
150 mvfr0.advSimdRegisters = 2;
151 mvfr0.singlePrecision = 2;
152 mvfr0.doublePrecision = 2;
153 mvfr0.vfpExceptionTrapping = 0;
154 mvfr0.divide = 1;
155 mvfr0.squareRoot = 1;
156 mvfr0.shortVectors = 1;
157 mvfr0.roundingModes = 1;
158 miscRegs[MISCREG_MVFR0] = mvfr0;
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