Searched refs:miss (Results 1 - 21 of 21) sorted by relevance

/gem5/ext/mcpat/
H A Dcachearray.h99 // Write miss on dynamic home node will generate a replacement write on
105 sbt_stats_p->readAc.miss *
107 sbt_stats_p->writeAc.miss *
112 sbt_stats_p->writeAc.miss *
H A Dbasic_components.h118 double miss; member in class:statsComponents
120 statsComponents() : access(0), hit(0), miss(0) {}
127 miss = rhs.miss;
133 miss = 0;
H A Dbasic_components.cc330 z.miss = x.miss + y.miss;
340 z.miss = x.miss * y[2];
H A Dcacheunit.cc137 arrayPtr->tdp_stats.readAc.miss = 0;
139 arrayPtr->tdp_stats.readAc.miss;
143 arrayPtr->tdp_stats.writeAc.miss = 0;
145 arrayPtr->tdp_stats.writeAc.miss;
147 arrayPtr->tdp_stats.searchAc.miss = 0;
185 arrayPtr->sbt_tdp_stats.readAc.miss = 0;
188 arrayPtr->sbt_tdp_stats.readAc.miss;
193 arrayPtr->sbt_tdp_stats.writeAc.miss = 0;
196 arrayPtr->sbt_tdp_stats.writeAc.miss;
201 arrayPtr->sbt_rtp_stats.readAc.miss
[all...]
H A Dcachearray.cc274 tdp_stats.readAc.miss +
279 tdp_stats.writeAc.miss;
H A Dcore.cc131 * look up table than a cache with cache controller. When access miss, no load from other places
718 * there is no change to flush miss-predict branch path after instructions are issued in this situation.
3117 itlb->tdp_stats.readAc.miss = 0;
3119 itlb->tdp_stats.readAc.miss;
3128 itlb->tdp_stats.readAc.miss *
3140 dtlb->tdp_stats.readAc.miss = 0;
3142 dtlb->tdp_stats.readAc.miss;
3153 dtlb->tdp_stats.readAc.miss *
/gem5/src/mem/cache/prefetch/
H A Dbase.hh76 parent(_parent), isFill(_isFill), miss(_miss) {}
81 const bool miss; member in class:BasePrefetcher::PrefetchListener
109 /** Whether this event comes from a cache miss */
190 * Check if this event comes from a cache miss
191 * @result true if this event comes from a cache miss
238 * @param miss whether this event comes from a cache miss
240 PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
298 * @param miss whether this event comes from a cache miss
[all...]
H A Dbase.cc59 BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool miss) argument
63 paddress(pkt->req->getPaddr()), cacheMiss(miss)
66 if (!write && miss) {
88 parent.probeNotify(pkt, miss);
127 BasePrefetcher::observeAccess(const PacketPtr &pkt, bool miss) const
142 return miss;
203 BasePrefetcher::probeNotify(const PacketPtr &pkt, bool miss) argument
219 if (observeAccess(pkt, miss)) {
221 PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
224 PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss);
[all...]
H A Dsignature_path.cc162 stride_t block, bool &miss, stride_t &stride,
168 miss = false;
179 miss = true;
239 bool miss; local
241 current_block, miss, stride, initial_confidence);
243 if (miss) {
161 getSignatureEntry(Addr ppn, bool is_secure, stride_t block, bool &miss, stride_t &stride, double &initial_confidence) argument
H A Dindirect_memory.cc72 bool miss = pfi.isCacheMiss(); local
76 // First check if this is a miss, if the prefetcher is tracking misses
77 if (ipdEntryTrackingMisses != nullptr && miss) {
109 if (!miss && !pfi.isWrite() && pfi.getSize() <= 8) {
H A Dsignature_path.hh184 * @param miss if the entry is not found, this will be set to true
190 bool &miss, stride_t &stride, double &initial_confidence);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/
H A Damoadd_d.S26 # try again after a cache miss
H A Damoadd_w.S26 # try again after a cache miss
H A Damoand_d.S26 # try again after a cache miss
H A Damoand_w.S26 # try again after a cache miss
H A Damoor_d.S26 # try again after a cache miss
H A Damoor_w.S26 # try again after a cache miss
H A Damoswap_d.S26 # try again after a cache miss
H A Damoswap_w.S26 # try again after a cache miss
H A Damoxor_d.S26 # try again after a cache miss
H A Damoxor_w.S26 # try again after a cache miss

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