Searched refs:log2 (Results 1 - 20 of 20) sorted by relevance

/gem5/ext/systemc/src/sysc/utils/
H A Dsc_temporary.h133 // sc_vpool( int log2, T* pool_p=0 )
135 // the object to manage a vector of 2**log2 entries. If a vector is
137 // log2 = the log base two of the size of the vector.
138 // pool_p -> vector of 2**log2 entries to be managed or 0.
168 inline sc_vpool( int log2, T* pool_p=0 );
175 template<class T> sc_vpool<T>::sc_vpool( int log2, T* pool_p ) argument
177 , m_pool_p( pool_p ? pool_p : new T[static_cast<std::size_t>(1) << log2] )
178 , m_wrap( ~(static_cast<std::size_t>(-1) << log2) )
180 // if ( log2 > 32 ) SC_REPORT_ERROR(SC_ID_POOL_SIZE_, "");
/gem5/src/systemc/ext/dt/
H A Dsc_temporary.hh130 // sc_vpool( int log2, T* pool_p=0 )
132 // the object to manage a vector of 2**log2 entries. If a vector is
134 // log2 = the log base two of the size of the vector.
135 // pool_p -> vector of 2**log2 entries to be managed or 0.
166 inline sc_vpool(int log2, T *pool_p=0);
174 sc_vpool<T>::sc_vpool(int log2, T *pool_p) : m_pool_i(0), argument
175 m_pool_p(pool_p ? pool_p : new T[static_cast<std::size_t>(1) << log2]),
176 m_wrap(~(static_cast<std::size_t>(-1) << log2))
178 // if (log2 > 32) SC_REPORT_ERROR(SC_ID_POOL_SIZE_, "");
/gem5/src/mem/cache/compressors/
H A Dbase.cc105 compressionSize[std::ceil(std::log2(comp_size_bits))]++;
157 .init(std::log2(blkSize*8) + 2)
163 for (unsigned i = 0; i <= std::log2(blkSize*8) + 1; ++i) {
H A Dbdi.cc169 size += bitMask.size()*std::ceil(std::log2(maxNumBases));
/gem5/ext/dsent/model/electrical/
H A DMultiplexer.cc70 unsigned int number_selects = (unsigned int) ceil(log2((double) number_inputs));
96 unsigned int selects_0 = (unsigned int) ceil(log2((double) inputs_0));
99 unsigned int selects_1 = (unsigned int) ceil(log2((double) inputs_1));
277 unsigned int number_selects = (unsigned int) ceil(log2((double) number_inputs));
283 unsigned int selects_0 = (unsigned int) ceil(log2((double) inputs_0));
287 unsigned int selects_1 = (unsigned int) ceil(log2((double) inputs_1));
H A DBarrelShifter.cc70 unsigned int number_shift_bits = (unsigned int)ceil(log2((double) number_bits));
202 unsigned int number_shift_bits = (unsigned int) ceil(log2((double) number_bits));
H A DDecoder.cc69 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_outputs));
201 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_outputs));
H A DDFFRAM.cc79 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_entries));
281 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_entries));
H A DMultiplexerCrossbar.cc80 unsigned int number_selects = (unsigned int)ceil(log2((double)number_inputs));
H A DMuxTreeSerializer.cc86 unsigned int number_stages = (unsigned int)ceil(log2((double) serialization_ratio));
/gem5/ext/dsent/model/optical/
H A DOpticalLinkBackendRx.cc139 unsigned int shift_index_min = (unsigned int)ceil(log2(deserialization_ratio));
140 unsigned int shift_index_max = std::max(shift_index_min, (unsigned int) ceil(log2(out_bits)) - 1);
218 unsigned int reorder_sel_bits = (unsigned int)ceil(log2(reorder_degree));
H A DOpticalLinkBackendTx.cc126 unsigned int shift_index_min = (unsigned int)ceil(log2(serialization_ratio));
127 unsigned int shift_index_max = std::max(shift_index_min, (unsigned int) ceil(log2(in_bits)) - 1);
226 unsigned int reorder_sel_bits = (unsigned int)ceil(log2(reorder_degree));
/gem5/ext/mcpat/cacti/
H A Dparameter.cc294 tagbits = ADDRESS_BITS + EXTRA_TAG_BITS - _log2(g_ip->block_sz);//TODO: should be the page_offset=log2(page size), but this info is not avail with CACTI, for McPAT this is no problem.
439 num_so_b_mat = int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays)));//the address contains the matched data
490 num_so_b_subbank = int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays)));//the address contains the matched data
568 number_subbanks_decode = _log2(number_subbanks);//TODO: add log2(num_subarray_per_bank) to FA/CAM
602 num_so_b_bank_per_port = int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays)));
H A Dbasic_circuit.cc44 uint32_t log2 = 0; local
53 log2++;
56 return log2;
/gem5/ext/dsent/model/electrical/router/
H A DRouterInputPort.cc109 unsigned int number_addr_bits = (unsigned int)ceil(log2(total_number_bufs));
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.cc209 int num_bits = (int) log2(num_destinations);
/gem5/ext/pybind11/include/pybind11/detail/
H A Dcommon.h355 inline static constexpr int log2(size_t n, int k = 0) { return (n <= 1) ? k : log2(n >> 1, k + 1); } function
358 inline static constexpr size_t size_in_ptrs(size_t s) { return 1 + ((s - 1) >> log2(sizeof(void *))); }
695 std::is_integral<T>::value ? detail::log2(sizeof(T))*2 + std::is_unsigned<T>::value : 8 + (
/gem5/ext/mcpat/
H A Dcore.cc143 idx = int(ceil(log2(size / line / assoc)));
144 tag = virtual_address_width + int(ceil(log2(core_params.num_hthreads)))
302 tag = int(log2(core_params.num_hthreads) + EXTRA_TAG_BITS);
527 tag = int(log2(core_params.num_hthreads) * core_params.perThreadState);
727 log2(core_params.num_hthreads)));
836 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
870 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
929 tag = virtual_address_width - int(floor(log2(virtual_memory_page_size))) +
930 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS;
931 data = physical_address_width - int(floor(log2(virtual_memory_page_siz
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H A Dcacheunit.cc82 tag = physical_address_width - int(ceil(log2(size / line / assoc))) -
83 int(ceil(log2(line))) + EXTRA_TAG_BITS;
223 int(ceil(log2(size / cache_params.blockW))) +
/gem5/ext/drampower/src/
H A DCmdScheduler.cc40 #include <cmath> // For log2
658 return static_cast<uint64_t>(log2(in));

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