Searched refs:log2 (Results 1 - 20 of 20) sorted by relevance
/gem5/ext/systemc/src/sysc/utils/ |
H A D | sc_temporary.h | 133 // sc_vpool( int log2, T* pool_p=0 ) 135 // the object to manage a vector of 2**log2 entries. If a vector is 137 // log2 = the log base two of the size of the vector. 138 // pool_p -> vector of 2**log2 entries to be managed or 0. 168 inline sc_vpool( int log2, T* pool_p=0 ); 175 template<class T> sc_vpool<T>::sc_vpool( int log2, T* pool_p ) argument 177 , m_pool_p( pool_p ? pool_p : new T[static_cast<std::size_t>(1) << log2] ) 178 , m_wrap( ~(static_cast<std::size_t>(-1) << log2) ) 180 // if ( log2 > 32 ) SC_REPORT_ERROR(SC_ID_POOL_SIZE_, "");
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/gem5/src/systemc/ext/dt/ |
H A D | sc_temporary.hh | 130 // sc_vpool( int log2, T* pool_p=0 ) 132 // the object to manage a vector of 2**log2 entries. If a vector is 134 // log2 = the log base two of the size of the vector. 135 // pool_p -> vector of 2**log2 entries to be managed or 0. 166 inline sc_vpool(int log2, T *pool_p=0); 174 sc_vpool<T>::sc_vpool(int log2, T *pool_p) : m_pool_i(0), argument 175 m_pool_p(pool_p ? pool_p : new T[static_cast<std::size_t>(1) << log2]), 176 m_wrap(~(static_cast<std::size_t>(-1) << log2)) 178 // if (log2 > 32) SC_REPORT_ERROR(SC_ID_POOL_SIZE_, "");
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/gem5/src/mem/cache/compressors/ |
H A D | base.cc | 105 compressionSize[std::ceil(std::log2(comp_size_bits))]++; 157 .init(std::log2(blkSize*8) + 2) 163 for (unsigned i = 0; i <= std::log2(blkSize*8) + 1; ++i) {
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H A D | bdi.cc | 169 size += bitMask.size()*std::ceil(std::log2(maxNumBases));
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/gem5/ext/dsent/model/electrical/ |
H A D | Multiplexer.cc | 70 unsigned int number_selects = (unsigned int) ceil(log2((double) number_inputs)); 96 unsigned int selects_0 = (unsigned int) ceil(log2((double) inputs_0)); 99 unsigned int selects_1 = (unsigned int) ceil(log2((double) inputs_1)); 277 unsigned int number_selects = (unsigned int) ceil(log2((double) number_inputs)); 283 unsigned int selects_0 = (unsigned int) ceil(log2((double) inputs_0)); 287 unsigned int selects_1 = (unsigned int) ceil(log2((double) inputs_1));
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H A D | BarrelShifter.cc | 70 unsigned int number_shift_bits = (unsigned int)ceil(log2((double) number_bits)); 202 unsigned int number_shift_bits = (unsigned int) ceil(log2((double) number_bits));
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H A D | Decoder.cc | 69 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_outputs)); 201 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_outputs));
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H A D | DFFRAM.cc | 79 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_entries)); 281 unsigned int number_addr_bits = (unsigned int)ceil(log2(number_entries));
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H A D | MultiplexerCrossbar.cc | 80 unsigned int number_selects = (unsigned int)ceil(log2((double)number_inputs));
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H A D | MuxTreeSerializer.cc | 86 unsigned int number_stages = (unsigned int)ceil(log2((double) serialization_ratio));
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/gem5/ext/dsent/model/optical/ |
H A D | OpticalLinkBackendRx.cc | 139 unsigned int shift_index_min = (unsigned int)ceil(log2(deserialization_ratio)); 140 unsigned int shift_index_max = std::max(shift_index_min, (unsigned int) ceil(log2(out_bits)) - 1); 218 unsigned int reorder_sel_bits = (unsigned int)ceil(log2(reorder_degree));
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H A D | OpticalLinkBackendTx.cc | 126 unsigned int shift_index_min = (unsigned int)ceil(log2(serialization_ratio)); 127 unsigned int shift_index_max = std::max(shift_index_min, (unsigned int) ceil(log2(in_bits)) - 1); 226 unsigned int reorder_sel_bits = (unsigned int)ceil(log2(reorder_degree));
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/gem5/ext/mcpat/cacti/ |
H A D | parameter.cc | 294 tagbits = ADDRESS_BITS + EXTRA_TAG_BITS - _log2(g_ip->block_sz);//TODO: should be the page_offset=log2(page size), but this info is not avail with CACTI, for McPAT this is no problem. 439 num_so_b_mat = int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays)));//the address contains the matched data 490 num_so_b_subbank = int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays)));//the address contains the matched data 568 number_subbanks_decode = _log2(number_subbanks);//TODO: add log2(num_subarray_per_bank) to FA/CAM 602 num_so_b_bank_per_port = int(ceil(log2(num_r_subarray)) + ceil(log2(num_subarrays)));
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H A D | basic_circuit.cc | 44 uint32_t log2 = 0; local 53 log2++; 56 return log2;
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/gem5/ext/dsent/model/electrical/router/ |
H A D | RouterInputPort.cc | 109 unsigned int number_addr_bits = (unsigned int)ceil(log2(total_number_bufs));
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/gem5/src/cpu/testers/garnet_synthetic_traffic/ |
H A D | GarnetSyntheticTraffic.cc | 209 int num_bits = (int) log2(num_destinations);
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/gem5/ext/pybind11/include/pybind11/detail/ |
H A D | common.h | 355 inline static constexpr int log2(size_t n, int k = 0) { return (n <= 1) ? k : log2(n >> 1, k + 1); } function 358 inline static constexpr size_t size_in_ptrs(size_t s) { return 1 + ((s - 1) >> log2(sizeof(void *))); } 695 std::is_integral<T>::value ? detail::log2(sizeof(T))*2 + std::is_unsigned<T>::value : 8 + (
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/gem5/ext/mcpat/ |
H A D | core.cc | 143 idx = int(ceil(log2(size / line / assoc))); 144 tag = virtual_address_width + int(ceil(log2(core_params.num_hthreads))) 302 tag = int(log2(core_params.num_hthreads) + EXTRA_TAG_BITS); 527 tag = int(log2(core_params.num_hthreads) * core_params.perThreadState); 727 log2(core_params.num_hthreads))); 836 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 870 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 929 tag = virtual_address_width - int(floor(log2(virtual_memory_page_size))) + 930 int(ceil(log2(core_params.num_hthreads))) + EXTRA_TAG_BITS; 931 data = physical_address_width - int(floor(log2(virtual_memory_page_siz [all...] |
H A D | cacheunit.cc | 82 tag = physical_address_width - int(ceil(log2(size / line / assoc))) - 83 int(ceil(log2(line))) + EXTRA_TAG_BITS; 223 int(ceil(log2(size / cache_params.blockW))) +
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/gem5/ext/drampower/src/ |
H A D | CmdScheduler.cc | 40 #include <cmath> // For log2 658 return static_cast<uint64_t>(log2(in));
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