Searched refs:eventq_irq_cfg0 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dsmmu_v3_defs.hh150 uint64_t eventq_irq_cfg0; // 0x00b0, 64 bit member in struct:SMMURegs::__anon15
H A Dsmmu_v3_transl.cc1320 if (!(smmu.regs.eventq_irq_cfg0 & E_BASE_ENABLE_MASK))
1323 doWrite(yield, smmu.regs.eventq_irq_cfg0 & E_BASE_ADDR_MASK,
H A Dsmmu_v3.cc660 case offsetof(SMMURegs, eventq_irq_cfg0):

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