Searched refs:cu_id (Results 1 - 18 of 18) sorted by relevance

/gem5/src/gpu-compute/
H A Dshader.hh171 void AccessMem(uint64_t address, void *ptr, uint32_t size, int cu_id,
174 void ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id);
176 void ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id,
179 void WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id);
181 void WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id,
185 bool suppress_func_errors, int cu_id);
188 registerCU(int cu_id, ComputeUnit *compute_unit) argument
190 cuList[cu_id] = compute_unit;
196 void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);
H A Dshader.cc70 assert(i == cuList[i]->cu_id);
230 bool suppress_func_errors, int cu_id)
232 int block_size = cuList.at(cu_id)->cacheLineSize();
260 functionalTLBAccess(pkt1, cu_id, trans_mode);
261 functionalTLBAccess(pkt2, cu_id, trans_mode);
274 // fixme: this should be cuList[cu_id] if cu_id != n_cu
285 functionalTLBAccess(pkt, cu_id, trans_mode);
293 // fixme: this should be cuList[cu_id] if cu_id !
229 doFunctionalAccess(const RequestPtr &req, MemCmd cmd, void *data, bool suppress_func_errors, int cu_id) argument
334 AccessMem(uint64_t address, void *ptr, uint32_t size, int cu_id, MemCmd cmd, bool suppress_func_errors) argument
352 ReadMem(uint64_t address, void *ptr, uint32_t size, int cu_id) argument
358 ReadMem(uint64_t address, void *ptr, uint32_t size, int cu_id, bool suppress_func_errors) argument
365 WriteMem(uint64_t address, void *ptr,uint32_t size, int cu_id) argument
371 WriteMem(uint64_t address, void *ptr, uint32_t size, int cu_id, bool suppress_func_errors) argument
384 functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode) argument
[all...]
H A Dfetch_unit.cc133 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);
214 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
242 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
246 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
264 "%d bytes, %d instructions!\n", computeUnit->cu_id,
296 computeUnit->cu_id, wavefront->simdId,
H A Dcompute_unit.cc64 cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs),
289 cu_id, w->wgId, refCount);
306 "WF[%d][%d]\n", _n_wave, barrier_id, cu_id, w->simdId, w->wfSlotId);
450 DPRINTF(GPUSync, "CU%d: Checking for All At Barrier\n", cu_id);
479 cu_id, ccnt, bslots);
638 computeUnit->cu_id, w->simdId, w->wfSlotId,
648 computeUnit->cu_id, gpuDynInst->simdId,
676 computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId,
695 computeUnit->cu_id, gpuDynIns
[all...]
H A Dwavefront.cc360 computeUnit->cu_id, simdId, wfSlotId, ii->disassemble());
536 DPRINTF(GPUExec, "CU%d: WF[%d][%d]: Ready Inst : %s\n", computeUnit->cu_id,
657 "(pc: %i)\n", computeUnit->cu_id, simdId, wfSlotId, wfDynId,
796 computeUnit->cu_id, simdId, wfSlotId, wfDynId,
851 sizeof(computeUnit->cu_id) + sizeof(barrierId) + sizeof(initMask) +
867 *(int *)iter = computeUnit->cu_id; iter += sizeof(computeUnit->cu_id);
934 computeUnit->cu_id = *(int *)iter; iter += sizeof(computeUnit->cu_id);
H A Dglobal_memory_pipeline.cc149 computeUnit->cu_id, mp->simdId, mp->wfSlotId);
H A DGPU.py101 cu_id = Param.Int('CU id') variable in class:ComputeUnit
H A Dgpu_dyn_inst.cc158 cu->cu_id, simdId, wfSlotId, exec_mask);
H A Dgpu_dyn_inst.hh254 int cu_id; member in class:GPUDynInst
H A Dcompute_unit.hh137 int cu_id; member in class:ComputeUnit
/gem5/src/arch/hsail/insts/
H A Dmain.cc159 w->computeUnit->cu_id, w->wgId, refCount);
179 w->computeUnit->cu_id, w->simdId, w->wfSlotId, w->wfDynId);
H A Dmem_impl.hh238 m->cu_id = w->computeUnit->cu_id;
417 m->cu_id = w->computeUnit->cu_id;
586 m->cu_id = w->computeUnit->cu_id;
H A Dpseudo_inst.cc191 disassemble(), w->computeUnit->cu_id, w->simdId,
195 disassemble(), w->computeUnit->cu_id, w->simdId,
214 disassemble(), w->computeUnit->cu_id, w->simdId,
218 disassemble(), w->computeUnit->cu_id, w->simdId,
430 res_str += csprintf(" Executing on CU #%i\n", w->computeUnit->cu_id);
H A Ddecl.hh1133 gpuDynInst->cu_id = w->computeUnit->cu_id;
H A Dmem.hh551 "ld inst)\n", w->computeUnit->cu_id, w->simdId,
1531 "ld inst)\n", w->computeUnit->cu_id, w->simdId,
/gem5/src/arch/hsail/
H A Doperand.hh205 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
218 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
276 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx,
337 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx,
782 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane,
/gem5/tests/configs/
H A Dgpu-ruby.py201 compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
/gem5/configs/example/
H A Dapu_se.py230 compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,

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