Searched refs:cpacr (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/arm/
H A Dprocess.cc111 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); local
113 cpacr.cp10 = 0x3;
114 cpacr.cp11 = 0x3;
115 tc->setMiscReg(MISCREG_CPACR, cpacr);
133 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); local
135 cpacr.cp10 = 0x3;
136 cpacr.cp11 = 0x3;
138 cpacr.zen = 0x3;
139 tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc687 CPSR cpsr, CPACR cpacr) const
690 if ((el == EL0 && cpacr.fpen != 0x3) ||
691 (el == EL1 && !(cpacr.fpen & 0x1)))
699 CPSR cpsr, CPACR cpacr,
709 return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
711 uint8_t cpacr_cp10 = cpacr.cp10;
712 bool cpacr_asedis = cpacr.asedis;
1009 ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
1012 if ((el == EL0 && cpacr.zen != 0x3) ||
1013 (el == EL1 && !(cpacr
[all...]
H A Dmisc64.cc125 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); local
132 if ((el == EL0 && cpacr.fpen != 0x3) ||
133 (el == EL1 && !(cpacr.fpen & 0x1)))
H A Dstatic_inst.hh412 CPSR cpsr, CPACR cpacr) const;
421 CPSR cpsr, CPACR cpacr,
487 Fault checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const;

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