Searched refs:branch (Results 1 - 13 of 13) sorted by relevance

/gem5/util/maint/
H A Dcreate_patches.sh58 -u BRANCH Upstream branch
63 consumption from a git branch. By default, the script works on the
64 currently checked out branch (HEAD). When invoked, the script executes
67 1. Rebase the patches in the current branch onto the upstream
68 branch.
115 echo "Error: Patch branch '$BRANCH' doesn't exist" 1>&2
120 echo "Error: Upstream branch '$UPSTREAM' doesn't exist." 1>&2
128 echo "Upstream branch: $UPSTREAM"
134 # Create an exit trap to checkout the old branch when we're done
144 git filter-branch
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H A Dlist_changes.py108 def list_revs(branch, baseline=None, paths=[]):
109 """Get a generator that lists git revisions that exist in 'branch'. If
111 excludes commits that exist on that branch.
118 query = "%s..%s" % (branch, baseline)
120 query = str(branch)
163 description="List incoming and outgoing changes in a feature branch")
166 help="Upstream branch for comparison. " \
169 help="Feature branch for comparison. " \
/gem5/src/cpu/minor/
H A Dexecute.hh43 * All the fun of executing instructions from Decode and sending branch/new
193 * a branch, but it minimises disruption in stream identification */
216 /** Generate Branch data based (into branch) on an observed (or not)
218 * Also handles branch prediction information within the inst. */
219 void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch);
221 /** Actually create a branch to communicate to Fetch1/Fetch2 and,
222 * if that is a stream-changing branch update the streamSeqNum */
225 BranchData &branch);
231 * Sets branch to any branch generate
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H A Dpipe_data.cc153 operator <<(std::ostream &os, const BranchData &branch) argument
155 os << branch.reason << " target: 0x"
156 << std::hex << branch.target.instAddr() << std::dec
157 << ' ' << *branch.inst
158 << ' ' << branch.newStreamSeqNum << "(stream)."
159 << branch.newPredictionSeqNum << "(pred)";
H A Dexecute.cc216 Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) argument
222 /* Force a branch for SerializeAfter/SquashAfter instructions
239 /* The reason for the branch data we're about to generate, set below */
252 /* Predicted to branch */
254 /* No branch was taken, change stream to get us back to the
256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
262 /* Branch prediction got the right target, kill the branch and
264 * Note that this information to the branch predictor might get
265 * overwritten by a "real" branch during this cycle */
266 DPRINTF(Branch, "Predicted a branch fro
295 updateBranchData( ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch) argument
321 handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) argument
418 takeInterrupt(ThreadID thread_id, BranchData &branch) argument
448 executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &passed_predicate, Fault &fault) argument
890 commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue) argument
1023 commit(ThreadID thread_id, bool only_commit_microops, bool discard, BranchData &branch) argument
1418 BranchData &branch = *out.inputWire; local
1599 checkInterrupts(BranchData& branch, bool& interrupted) argument
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H A Dfetch2.cc126 Fetch2::updateBranchPrediction(const BranchData &branch) argument
128 MinorDynInstPtr inst = branch.inst;
134 switch (branch.reason) {
152 /* Unpredicted branch or barrier */
153 DPRINTF(Branch, "Unpredicted branch seen inst: %s\n", *inst);
155 branch.target, true, inst->id.threadId);
157 // using the branch prediction code.
171 branch.target /* Not used */, false, inst->id.threadId);
173 // using the branch prediction code.
180 *inst, branch
188 predictBranch(MinorDynInstPtr inst, BranchData &branch) argument
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H A Dfetch1.cc489 Fetch1::changeStream(const BranchData &branch) argument
491 Fetch1ThreadInfo &thread = fetchInfo[branch.threadId];
493 updateExpectedSeqNums(branch);
496 switch (branch.reason) {
501 branch);
503 DPRINTF(Fetch, "Suspending fetch: %s\n", branch);
513 DPRINTF(Fetch, "Changing stream on branch: %s\n", branch);
517 thread.pc = branch.target;
521 Fetch1::updateExpectedSeqNums(const BranchData &branch) argument
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H A Dfetch2.hh157 * represent predicted changes of control flow sources from branch
188 /** Update local branch prediction structures from feedback from
190 void updateBranchPrediction(const BranchData &branch);
193 * instruction's predicted... fields and also the branch which
195 void predictBranch(MinorDynInstPtr inst, BranchData &branch);
H A Dfetch1.hh194 /** Input port carrying branch requests from Execute */
198 /** Input port carrying branch predictions from Fetch2 */
260 /** Fetch PC value. This is updated by branches from Execute, branch
325 void changeStream(const BranchData &branch);
327 /** Update streamSeqNum and predictionSeqNum from the given branch (and
330 void updateExpectedSeqNums(const BranchData &branch);
406 * Execute signalling a branch with the reason HaltFetch */
H A Dpipe_data.hh69 /* *** No change of stream (information to branch prediction) */
71 /* Don't branch at all (bubble) */
73 /* Don't branch, but here's the details of a correct prediction
79 /* Take an unpredicted branch */
81 /* Take a branch on branch prediction data (from Fetch2) */
85 /* Bad branch prediction (didn't actually branch). Need to branch
90 * This will be woken up by another stream changing branch s
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/gem5/src/systemc/tests/systemc/examples/trie/
H A Dtrie.cpp112 sc_uint<5> branch; local
121 branch = BRANCH(t);
123 while(branch != 0){
124 addr = addr + extract(ip, pos, branch);
126 pos = pos - (branch + SKIP(t));
127 branch = BRANCH(t);
/gem5/system/alpha/console/
H A Ddbmentry.S174 blbs a1,2f # branch if lock is busy
176 beq v0,2f # branch if lost atomicity
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Dma_fetch.S81 # Like test 2, but with a taken branch instead of jalr.

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