| /gem5/src/arch/riscv/insts/ |
| H A D | mem.cc | 52 offset << '(' << registerName(_srcRegIdx[0]) << ')';
60 ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
61 offset << '(' << registerName(_srcRegIdx[0]) << ')';
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| H A D | amo.cc | 67 << registerName(_srcRegIdx[0]) << ')';
76 << registerName(_srcRegIdx[0]) << ')';
86 << registerName(_srcRegIdx[1]) << ", ("
87 << registerName(_srcRegIdx[0]) << ')';
96 << registerName(_srcRegIdx[1]) << ", ("
97 << registerName(_srcRegIdx[0]) << ')';
107 << registerName(_srcRegIdx[1]) << ", ("
108 << registerName(_srcRegIdx[0]) << ')';
117 << registerName(_srcRegIdx[1]) << ", ("
118 << registerName(_srcRegIdx[
[all...] |
| H A D | standard.cc | 51 registerName(_srcRegIdx[0]) << ", " <<
52 registerName(_srcRegIdx[1]);
62 ss << registerName(_srcRegIdx[0]) << ", ";
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| H A D | compressed.cc | 48 registerName(_srcRegIdx[0]);
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| /gem5/src/arch/power/insts/ |
| H A D | floating.cc | 52 printReg(ss, _srcRegIdx[0]);
55 printReg(ss, _srcRegIdx[1]);
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| H A D | misc.cc | 52 printReg(ss, _srcRegIdx[0]);
55 printReg(ss, _srcRegIdx[1]);
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| H A D | integer.cc | 48 if (!myMnemonic.compare("or") && _srcRegIdx[0] == _srcRegIdx[1]) {
72 printReg(ss, _srcRegIdx[0]);
75 printReg(ss, _srcRegIdx[1]);
109 printReg(ss, _srcRegIdx[0]);
136 printReg(ss, _srcRegIdx[0]);
163 printReg(ss, _srcRegIdx[0]);
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| H A D | mem.cc | 63 printReg(ss, _srcRegIdx[1]);
71 printReg(ss, _srcRegIdx[0]);
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| H A D | branch.cc | 156 uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index());
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| /gem5/src/arch/sparc/insts/ |
| H A D | trap.cc | 44 printReg(response, _srcRegIdx[0]);
47 printReg(response, _srcRegIdx[1]);
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| H A D | blockmem.cc | 46 printReg(response, _srcRegIdx[0]);
50 printReg(response, _srcRegIdx[!save ? 0 : 1]);
52 printReg(response, _srcRegIdx[!save ? 1 : 2]);
71 printReg(response, _srcRegIdx[1]);
75 printReg(response, _srcRegIdx[0]);
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| H A D | mem.cc | 47 printReg(response, _srcRegIdx[0]);
51 if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
74 printReg(response, _srcRegIdx[0]);
78 if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
79 printReg(response, _srcRegIdx[!save ? 0 : 1]);
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| H A D | integer.cc | 47 if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) {
62 if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
90 printRegArray(response, _srcRegIdx, _numSrcRegs);
105 printRegArray(response, _srcRegIdx, _numSrcRegs);
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| H A D | branch.cc | 52 printRegArray(response, _srcRegIdx, _numSrcRegs);
66 printRegArray(response, _srcRegIdx, _numSrcRegs);
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| H A D | priv.cc | 72 if (_srcRegIdx[0].index() != 0) {
92 if (_srcRegIdx[0].index() != 0) {
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| H A D | static_inst.cc | 86 printReg(os, _srcRegIdx[reg]);
261 printReg(ss, _srcRegIdx[0]);
264 printReg(ss, _srcRegIdx[1]);
|
| /gem5/src/cpu/o3/ |
| H A D | dyn_inst.hh | 107 using BaseDynInst<Impl>::_srcRegIdx;
273 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
279 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
285 return this->cpu->readVecReg(this->_srcRegIdx[idx]);
303 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
310 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
317 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
324 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
362 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
368 return this->cpu->readVecPredReg(this->_srcRegIdx[id
[all...] |
| /gem5/src/arch/x86/insts/ |
| H A D | static_inst.hh | 141 if (_srcRegIdx[idx].index() & IntFoldBit)
162 if (_srcRegIdx[idx].index() & IntFoldBit)
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| H A D | static_inst.cc | 112 printReg(os, _srcRegIdx[reg], size);
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| /gem5/src/cpu/ |
| H A D | static_inst.hh | 220 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
236 RegId _srcRegIdx[MaxInstSrcRegs]; member in class:StaticInst
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| H A D | base_dyn_inst.hh | 263 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; member in class:BaseDynInst
365 return _srcRegIdx[idx];
403 _srcRegIdx[idx] = renamed_src;
|