Searched refs:VectorRegisterFile (Results 1 - 6 of 6) sorted by relevance

/gem5/src/gpu-compute/
H A Dvector_register_file.cc47 #include "params/VectorRegisterFile.hh"
49 VectorRegisterFile::VectorRegisterFile(const VectorRegisterFileParams *p) function in class:VectorRegisterFile
70 VectorRegisterFile::setParent(ComputeUnit *_computeUnit)
77 VectorRegisterFile::regNxtBusy(int idx, uint32_t operandSize) const
89 VectorRegisterFile::regBusy(int idx, uint32_t operandSize) const
101 VectorRegisterFile::preMarkReg(int regIdx, uint32_t operandSize, uint8_t value)
111 VectorRegisterFile::markReg(int regIdx, uint32_t operandSize, uint8_t value)
121 VectorRegisterFile::operandsReady(Wavefront *w, GPUDynInstPtr ii) const
154 VectorRegisterFile
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H A Dvector_register_file.hh64 class VectorRegisterFile : public SimObject class in class:VrfAccessType
67 VectorRegisterFile(const VectorRegisterFileParams *p);
H A DGPU.py55 class VectorRegisterFile(SimObject): class in inherits:SimObject
56 type = 'VectorRegisterFile'
57 cxx_class = 'VectorRegisterFile'
136 vector_register_file = VectorParam.VectorRegisterFile("Vector register "\
H A Dcompute_unit.hh64 class VectorRegisterFile;
140 std::vector<VectorRegisterFile*> vrf;
/gem5/tests/configs/
H A Dgpu-ruby.py233 vrfs.append(VectorRegisterFile(simd_id=j,
/gem5/configs/example/
H A Dapu_se.py263 vrfs.append(VectorRegisterFile(simd_id=j,

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