Searched refs:MISCREG_TTBCR (Results 1 - 8 of 8) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc221 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
563 case MISCREG_TTBCR:
675 case MISCREG_TTBCR:
H A Disa.hh602 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
618 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
H A Disa.cc1742 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1785 case MISCREG_TTBCR:
1787 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
1824 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
H A Dmiscregs.hh195 MISCREG_TTBCR, enumerator in enum:ArmISA::MiscRegIndex
H A Dtlb.cc1370 ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
H A Dmiscregs.cc276 return MISCREG_TTBCR;
3247 InitReg(MISCREG_TTBCR)
H A Dtable_walker.cc296 MISCREG_TTBCR, currState->tc, !currState->isSecure));
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc802 } else if (reg == MISCREG_TTBCR) {

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