Searched refs:MISCREG_TSL_BASE (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/
H A Dfaults.cc265 tc->setMiscReg(MISCREG_TSL_BASE, 0);
H A Disa.cc288 case MISCREG_TSL_BASE:
/gem5/src/arch/x86/regs/
H A Dmisc.hh321 MISCREG_TSL_BASE, enumerator in enum:X86ISA::MiscRegIndex

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