Searched refs:MISCREG_SRSCTL (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/mips/
H A Dfaults.cc109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
112 tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
H A Dregisters.hh183 MISCREG_SRSCTL, enumerator in enum:MipsISA::MiscRegIndex
H A Disa.cc273 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
275 setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
279 setRegMask(MISCREG_SRSCTL, SC_Mask);

Completed in 9 milliseconds