Searched refs:MISCREG_MTRR_PHYS_MASK_2 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc58 MsrVal(0x205, MISCREG_MTRR_PHYS_MASK_2),
H A Dmisc.hh178 MISCREG_MTRR_PHYS_MASK_2, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc349 regNum = MISCREG_MTRR_PHYS_MASK_2;

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