Searched refs:MISCREG_MTRR_PHYS_BASE_5 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/regs/
H A Dmsr.cc63 MsrVal(0x20A, MISCREG_MTRR_PHYS_BASE_5),
H A Dmisc.hh170 MISCREG_MTRR_PHYS_BASE_5, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc364 regNum = MISCREG_MTRR_PHYS_BASE_5;

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