Searched refs:MISCREG_MMU_LSU_CTRL (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/sparc/
H A Dmiscregs.hh92 MISCREG_MMU_LSU_CTRL, enumerator in enum:SparcISA::MiscRegIndex
H A Dutility.cc163 dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
164 src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
H A Disa.cc297 case MISCREG_MMU_LSU_CTRL:
509 case MISCREG_MMU_LSU_CTRL:
H A Dprocess.cc157 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
H A Dtlb.cc875 pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
1071 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);

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