Searched refs:MISCREG_ICH_LR0_EL2 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc270 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
300 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
420 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
433 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
476 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
489 isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
692 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
715 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
841 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
920 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2
[all...]
/gem5/src/arch/arm/
H A Dmiscregs.hh740 MISCREG_ICH_LR0_EL2, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2523 return MISCREG_ICH_LR0_EL2;
4722 InitReg(MISCREG_ICH_LR0_EL2)

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