dev/arm/gic_v3_cpu_interface.cc

270                   isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
300                   isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
420                   isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
433                       isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
476                   isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
489                       isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
692                 isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
715       case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
841                   isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
920                   isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1498       case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
1635             isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
1861     ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1875     isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el);
1895     ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
1910     isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2);
2069             isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2121             isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
2160         isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2435             isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
2474             isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);