Searched refs:MISCREG_CTR_EL0 (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dmisc64.cc259 case MISCREG_CTR_EL0:
/gem5/src/arch/arm/
H A Dmiscregs.hh462 MISCREG_CTR_EL0, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc547 case MISCREG_CTR_EL0: // AArch64
H A Dmiscregs.cc1794 return MISCREG_CTR_EL0;
3965 InitReg(MISCREG_CTR_EL0)
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc423 { "ctr_el0", MISCREG_CTR_EL0 },

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