Searched refs:HW (Results 1 - 4 of 4) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.hh219 Bitfield<61> HW; member in class:Gicv3CPUInterface
236 Bitfield<29> HW; member in class:Gicv3CPUInterface
H A Dgic_v3_cpu_interface.cc695 (ich_lr_el2.HW || !ich_lr_el2.EOI)) {
1458 ich_lrc.HW = requested_ich_lrc.HW;
1469 // When ICH_LR<n>.HW is 0 this field has the following meaning:
1473 // When ICH_LR<n>.HW is 1:
1477 if (requested_ich_lrc.HW == 0) {
1503 ich_lr_el2.HW = requested_ich_lr_el2.HW;
1514 // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning:
1518 // When ICH_LR<n>_EL2.HW i
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H A Dvgic.hh47 * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
124 Bitfield<31> HW; member in class:VGic
H A Dvgic.cc120 // We don't support auto-EOI of HW interrupts via real GIC!
122 if (lr->HW)
123 panic("VGIC does not support 'HW' List Register feature (LR %#x)!\n",

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