Searched refs:vector (Results 276 - 300 of 763) sorted by relevance

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/gem5/util/systemc/gem5_within_systemc/
H A Dsc_gem5_control.hh58 #include <vector>
111 const std::vector<std::string> &param_values);
/gem5/src/mem/qos/
H A Dmem_sink.hh184 std::vector<PacketQueue> readQueue;
189 std::vector<PacketQueue> writeQueue;
/gem5/src/arch/arm/
H A Dsemihosting.cc90 const std::vector<const char *> ArmSemihosting::fmodes{
119 const std::vector<uint8_t> ArmSemihosting::features{
172 std::vector<uint64_t> argv(call->argc64 + 1);
207 std::vector<uint64_t> argv(call->argc32 + 1);
272 std::vector<char> buf(len + 1);
282 std::vector<uint64_t> &argv)
310 std::vector<uint64_t> &argv)
333 std::vector<uint64_t> &argv)
345 std::vector<uint64_t> &argv)
362 std::vector<uint64_
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/gem5/src/arch/riscv/
H A Dstacktrace.hh62 std::vector<Addr> stack;
93 const std::vector<Addr> &
/gem5/src/arch/power/
H A Dstacktrace.hh62 std::vector<Addr> stack;
93 const std::vector<Addr> &
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.hh35 #include <vector>
101 std::vector<MasterPort*> ports;
/gem5/src/cpu/pred/
H A Dtage_base.hh54 #include <vector>
429 std::vector<unsigned> tagTableTagWidths;
430 std::vector<int> logTagTableSizes;
432 std::vector<bool> btablePrediction;
433 std::vector<bool> btableHysteresis;
445 // @TODO Convert to std::vector<bool>
459 std::vector<ThreadHistory> threadHistory;
470 std::vector<int8_t> useAltPredForNewlyAllocated;
481 std::vector<bool> noSkip;
/gem5/src/sim/
H A Dsim_object.hh53 #include <vector>
100 typedef std::vector<SimObject *> SimObjectList;
H A Dprocess.hh41 #include <vector>
166 std::vector<ContextID> contextIds;
185 std::vector<std::string> argv;
186 std::vector<std::string> envp;
243 std::vector<EmulatedDriver *> drivers;
H A Dserialize.hh60 #include <vector>
411 const std::vector<T> &param)
413 typename std::vector<T>::size_type size = param.size();
417 for (typename std::vector<T>::size_type i = 1; i < size; ++i) {
500 std::vector<std::string> tokens;
504 // Need this if we were doing a vector
511 for (std::vector<std::string>::size_type i = 0; i < tokens.size(); i++) {
512 // need to parse into local variable to handle vector<bool>,
515 // vector)
526 // assign parsed value to vector
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/gem5/src/base/filters/
H A Dbase.hh35 #include <vector>
52 std::vector<SatCounter> filter;
/gem5/src/dev/x86/
H A Di82094aa.hh64 Bitfield<7, 0> vector; member in class:X86ISA::I82094AA
85 std::vector<IntSinkPin<I82094AA> *> inputs;
H A Di8259.hh51 std::vector<IntSourcePin<I8259> *> output;
52 std::vector<IntSinkPin<I8259> *> inputs;
63 // The higher order bits of the vector to return
67 // A bit vector of lines with slaves attached, or the slave id, depending
/gem5/ext/googletest/googlemock/test/
H A Dgmock-generated-matchers_test.cc42 #include <vector>
55 using std::vector;
289 Matcher<const vector<int>&> m = ElementsAre();
294 Matcher<vector<int> > m = ElementsAre(Gt(5));
306 Matcher<vector<int> > m = ElementsAre();
333 Matcher<const vector<int>& > m =
337 vector<int> test_vector(a, a + GTEST_ARRAY_SIZE_(a));
355 Matcher<const vector<int>& > m = ElementsAre(1, GreaterThan(5));
357 vector<int> v;
368 vector<strin
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/gem5/ext/pybind11/tests/
H A Dpybind11_cross_module_tests.cpp89 py::bind_vector<std::vector<int>>(m, "VectorInt");
91 m.def("load_vector_via_binding", [](std::vector<int> &v) {
113 // We can't test both stl.h and stl_bind.h conversions of `std::vector<bool>` within
116 py::bind_vector<std::vector<bool>>(m, "VectorBool");
121 m.def("missing_header_arg", [](std::vector<float>) { });
122 m.def("missing_header_return", []() { return std::vector<float>(); });
/gem5/src/base/
H A Dcirclebuf.hh45 #include <vector>
52 * Circular buffer backed by a vector though a CircularQueue.
55 * vector.
179 std::vector<T> temp(param.size());
189 std::vector<T> temp;
201 std::vector<T> temp(param.size());
211 std::vector<T> temp;
H A Dcoroutine.test.cc89 const std::vector<int> input{ 1, 2, 3 };
90 const std::vector<int> expected_values = input;
119 const std::vector<int> output{ 1, 2, 3 };
120 const std::vector<int> expected_values = output;
148 const std::vector<int> expected_values{
/gem5/src/arch/x86/
H A Dinterrupts.cc225 X86ISA::Interrupts::requestInterrupt(uint8_t vector, argument
238 if (vector > IRRV)
239 IRRV = vector;
240 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
241 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
243 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
245 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
253 smiVector = vector;
256 nmiVector = vector;
259 extIntVector = vector;
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/gem5/src/systemc/tests/systemc/compliance_1666/test203a/
H A Dtest203a.cpp19 std::vector<sc_object*> children = h.get_child_objects();
61 std::vector<sc_object*> children = this->get_child_objects();
74 std::vector<sc_object*> children2 = h2.get_child_objects();
90 std::vector<sc_object*> children3 = h3.get_child_objects();
120 std::vector<sc_object*> children3 = h3.get_child_objects();
144 std::vector<sc_object*> children3 = h3.get_child_objects();
168 std::vector<sc_object*> children3 = h3.get_child_objects();
190 std::vector<sc_object*> children3 = h3.get_child_objects();
212 std::vector<sc_object*> children2 = h2.get_child_objects();
231 std::vector<sc_objec
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/gem5/ext/dsent/model/electrical/router/
H A DRouterInputPort.cc25 #include <vector>
37 using std::vector;
75 const vector<unsigned int>& number_vcs_per_vn_vector = castStringVector<unsigned int>(getParameter("NumberVirtualChannelsPerVirtualNetwork").split("[,]"));
76 const vector<unsigned int>& number_bufs_per_vc_vector = castStringVector<unsigned int>(getParameter("NumberBuffersPerVirtualChannel").split("[,]"));
136 vector<String> rd_addr_dff_names(number_addr_bits, "");
137 vector<StdCell*> rd_addr_dffs(number_addr_bits, NULL);
192 vector<ElectricalModel*> rd_addr_dffs(number_addr_bits, NULL);
/gem5/src/gpu-compute/
H A Dwavefront.hh43 #include <vector>
180 // map virtual to physical vector register
192 std::vector<Addr> lastAddr;
193 std::vector<uint32_t> workItemId[3];
194 std::vector<uint32_t> workItemFlatId;
229 // number of vector registers reserved by WF
236 std::vector<uint32_t> oldVgpr;
243 std::vector<uint64_t> oldDgpr;
253 std::vector<int> barCnt;
266 // The vector widt
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/gem5/src/mem/
H A Dcoherent_xbar.hh78 * Declare the layers of this crossbar, one vector for requests,
81 std::vector<ReqLayer*> reqLayers;
82 std::vector<RespLayer*> respLayers;
83 std::vector<SnoopRespLayer*> snoopLayers;
253 std::vector<SnoopRespPort*> snoopRespPorts;
255 std::vector<QueuedSlavePort*> snoopPorts;
332 const std::vector<QueuedSlavePort*>& dests);
370 const std::vector<QueuedSlavePort*>&
/gem5/ext/dsent/model/electrical/
H A DDFFRAM.cc114 vector<String> dff_names(number_entries, "");
115 vector<StdCell*> dffs(number_entries, NULL);
144 vector<String> nand2cg1_names(number_entries, "");
145 vector<StdCell*> nand2cg1s(number_entries, NULL);
146 vector<String> invcg1_names(number_entries, "");
147 vector<StdCell*> invcg1s(number_entries, NULL);
301 vector<ElectricalModel*> nand2cg1s(number_entries, NULL);
302 vector<ElectricalModel*> invcg1s(number_entries, NULL);
316 vector<ElectricalModel*> dffs(number_entries, NULL);
/gem5/src/cpu/
H A Dtiming_expr.hh83 std::vector<uint64_t> results;
84 std::vector<bool > resultAvailable;
142 std::vector<TimingExpr *> defns;
/gem5/ext/dsent/model/optical_graph/
H A DOpticalWavelength.cc41 m_data_paths_ = new vector<OpticalDataPath>;
90 const vector<OpticalDataPath>* OpticalWavelength::getDataPaths() const
92 return (const vector<OpticalDataPath>*) m_data_paths_;

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