Searched refs:override (Results 201 - 225 of 403) sorted by relevance

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/gem5/src/dev/pci/
H A Dcopy_engine.hh109 DrainState drain() override; member in class:CopyEngine::CopyEngineChannel
110 void drainResume() override; member in class:CopyEngine::CopyEngineChannel
112 void serialize(CheckpointOut &cp) const override; member in class:CopyEngine::CopyEngineChannel
113 void unserialize(CheckpointIn &cp) override; member in class:CopyEngine::CopyEngineChannel
194 void regStats() override; member in class:CopyEngine
197 PortID idx = InvalidPortID) override; member in class:CopyEngine
199 Tick read(PacketPtr pkt) override; member in class:CopyEngine
200 Tick write(PacketPtr pkt) override; member in class:CopyEngine
202 void serialize(CheckpointOut &cp) const override; member in class:CopyEngine
203 void unserialize(CheckpointIn &cp) override; member in class:CopyEngine
[all...]
/gem5/src/systemc/tests/systemc/datatypes/fx/observers/
H A Dobservers.cpp25 # define override /* empty */ macro
30 virtual void construct(const Observed&) override {
33 virtual void destruct(const Observed&) override {
36 virtual void read(const Observed&) override {
39 virtual void write(const Observed&) override {
/gem5/src/dev/arm/
H A Dpl011.hh63 void serialize(CheckpointOut &cp) const override; member in class:Pl011
64 void unserialize(CheckpointIn &cp) override; member in class:Pl011
67 Tick read(PacketPtr pkt) override; member in class:Pl011
68 Tick write(PacketPtr pkt) override; member in class:Pl011
71 void dataAvailable() override; member in class:Pl011
H A Dsmmu_v3.hh173 virtual void init() override; member in class:SMMUv3
174 virtual void regStats() override; member in class:SMMUv3
187 DrainState drain() override; member in class:SMMUv3
188 void serialize(CheckpointOut &cp) const override; member in class:SMMUv3
189 void unserialize(CheckpointIn &cp) override; member in class:SMMUv3
192 PortID id = InvalidPortID) override; member in class:SMMUv3
H A Dgic_v2.hh201 void serialize(CheckpointOut &cp) const override; member in struct:GicV2::BankedRegs
202 void unserialize(CheckpointIn &cp) override; member in struct:GicV2::BankedRegs
449 DrainState drain() override;
450 void drainResume() override;
452 void serialize(CheckpointOut &cp) const override;
453 void unserialize(CheckpointIn &cp) override;
456 AddrRangeList getAddrRanges() const override { return addrRanges; }
461 Tick read(PacketPtr pkt) override;
466 Tick write(PacketPtr pkt) override;
469 void sendInt(uint32_t number) override;
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/gem5/src/arch/arm/tracers/
H A Dtarmac_record_v8.hh85 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecordV8::TraceInstEntryV8
102 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecordV8::TraceRegEntryV8
106 RegIndex regRelIdx) override; member in struct:Trace::TarmacTracerRecordV8::TraceRegEntryV8
109 RegIndex regRelIdx) override; member in struct:Trace::TarmacTracerRecordV8::TraceRegEntryV8
125 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecordV8::TraceMemEntryV8
/gem5/src/gpu-compute/
H A Dgpu_static_inst.hh274 execute(GPUDynInstPtr gpuDynInst) override
280 generateDisassembly() override
285 int getNumOperands() override { return 0; }
286 bool isCondRegister(int operandIndex) override { return false; }
287 bool isScalarRegister(int operandIndex) override { return false; }
288 bool isVectorRegister(int operandIndex) override { return false; }
289 bool isSrcOperand(int operandIndex) override { return false; }
290 bool isDstOperand(int operandIndex) override { return false; }
291 int getOperandSize(int operandIndex) override { return 0; }
294 getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
[all...]
/gem5/src/dev/storage/
H A Dide_ctrl.hh152 Tick writeConfig(PacketPtr pkt) override; member in class:IdeController
153 Tick readConfig(PacketPtr pkt) override; member in class:IdeController
157 Tick read(PacketPtr pkt) override; member in class:IdeController
158 Tick write(PacketPtr pkt) override; member in class:IdeController
160 void serialize(CheckpointOut &cp) const override; member in class:IdeController
161 void unserialize(CheckpointIn &cp) override; member in class:IdeController
/gem5/src/mem/cache/prefetch/
H A Dqueued.hh121 void markDelayed() override
125 ThreadContext *tc, BaseTLB::Mode mode) override; member in struct:QueuedPrefetcher::DeferredPacket
182 void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override; member in class:QueuedPrefetcher
188 PacketPtr getPacket() override; member in class:QueuedPrefetcher
190 Tick nextPrefetchReadyTime() const override
195 void regStats() override; member in class:QueuedPrefetcher
H A Ddelta_correlating_prediction_tables.hh83 void reset() override; member in struct:DeltaCorrelatingPredictionTables::DCPTEntry
135 std::vector<AddrPriority> &addresses) override; member in class:DCPTPrefetcher
/gem5/src/mem/
H A Dxbar.hh117 DrainState drain() override; member in class:BaseXBar::Layer
257 sendRetry(SlavePort* retry_port) override
280 sendRetry(MasterPort* retry_port) override
304 sendRetry(SlavePort* retry_port) override
413 PortID idx=InvalidPortID) override; member in class:BaseXBar
415 void regStats() override; member in class:BaseXBar
/gem5/src/dev/x86/
H A Di8042.hh132 getPort(const std::string &if_name, PortID idx=InvalidPortID) override
142 AddrRangeList getAddrRanges() const override; member in class:X86ISA::I8042
144 Tick read(PacketPtr pkt) override; member in class:X86ISA::I8042
146 Tick write(PacketPtr pkt) override; member in class:X86ISA::I8042
148 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::I8042
149 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::I8042
/gem5/src/arch/arm/insts/
H A Dmem64.hh62 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::SysDC64
119 fetchMicroop(MicroPC microPC) const override
143 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryImm64
159 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryDImm64
175 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryDImmEx64
188 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryPreIndex64
201 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryPostIndex64
220 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryReg64
232 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryRaw64
247 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryEx64
261 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::MemoryLiteral64
[all...]
H A Dmisc.hh56 Addr pc, const SymbolTable *symtab) const override; member in class:MrsOp
83 Addr pc, const SymbolTable *symtab) const override; member in class:MsrImmOp
97 Addr pc, const SymbolTable *symtab) const override; member in class:MsrRegOp
116 Addr pc, const SymbolTable *symtab) const override; member in class:MrrcOp
135 Addr pc, const SymbolTable *symtab) const override; member in class:McrrOp
149 Addr pc, const SymbolTable *symtab) const override; member in class:ImmOp
164 Addr pc, const SymbolTable *symtab) const override; member in class:RegImmOp
179 Addr pc, const SymbolTable *symtab) const override; member in class:RegRegOp
196 Addr pc, const SymbolTable *symtab) const override; member in class:RegImmRegOp
215 Addr pc, const SymbolTable *symtab) const override; member in class:RegRegRegImmOp
234 Addr pc, const SymbolTable *symtab) const override; member in class:RegRegRegRegOp
251 Addr pc, const SymbolTable *symtab) const override; member in class:RegRegRegOp
269 Addr pc, const SymbolTable *symtab) const override; member in class:RegRegImmOp
287 Addr pc, const SymbolTable *symtab) const override; member in class:MiscRegRegImmOp
305 Addr pc, const SymbolTable *symtab) const override; member in class:RegMiscRegImmOp
322 Addr pc, const SymbolTable *symtab) const override; member in class:RegImmImmOp
341 Addr pc, const SymbolTable *symtab) const override; member in class:RegRegImmImmOp
362 Addr pc, const SymbolTable *symtab) const override; member in class:RegImmRegShiftOp
374 Addr pc, const SymbolTable *symtab) const override; member in class:UnknownOp
394 Trace::InstRecord *traceData) const override; member in class:McrMrcMiscInst
397 Addr pc, const SymbolTable *symtab) const override; member in class:McrMrcMiscInst
412 Trace::InstRecord *traceData) const override; member in class:McrMrcImplDefined
415 Addr pc, const SymbolTable *symtab) const override; member in class:McrMrcImplDefined
[all...]
/gem5/src/arch/arm/
H A Dpmu.hh108 void serialize(CheckpointOut &cp) const override; member in class:ArmISA::PMU
109 void unserialize(CheckpointIn &cp) override; member in class:ArmISA::PMU
111 void drainResume() override; member in class:ArmISA::PMU
113 void regProbeListeners() override; member in class:ArmISA::PMU
116 void setThreadContext(ThreadContext *tc) override; member in class:ArmISA::PMU
124 void setMiscReg(int misc_reg, RegVal val) override; member in class:ArmISA::PMU
131 RegVal readMiscReg(int misc_reg) override; member in class:ArmISA::PMU
382 void enable() override; member in struct:ArmISA::PMU::RegularEvent
384 void disable() override; member in struct:ArmISA::PMU::RegularEvent
389 void enable() override {}
419 void serialize(CheckpointOut &cp) const override; member in struct:ArmISA::PMU::CounterState
420 void unserialize(CheckpointIn &cp) override; member in struct:ArmISA::PMU::CounterState
[all...]
/gem5/src/cpu/simple/
H A Dtiming.hh58 void init() override; member in class:TimingSimpleCPU
267 Port &getDataPort() override { return dcachePort; }
270 Port &getInstPort() override { return icachePort; }
274 DrainState drain() override; member in class:TimingSimpleCPU
275 void drainResume() override; member in class:TimingSimpleCPU
277 void switchOut() override; member in class:TimingSimpleCPU
278 void takeOverFrom(BaseCPU *oldCPU) override; member in class:TimingSimpleCPU
280 void verifyMemoryMode() const override; member in class:TimingSimpleCPU
282 void activateContext(ThreadID thread_num) override; member in class:TimingSimpleCPU
283 void suspendContext(ThreadID thread_num) override; member in class:TimingSimpleCPU
288 override; member in class:TimingSimpleCPU
293 override; member in class:TimingSimpleCPU
296 AtomicOpFunctorPtr amo_op) override; member in class:TimingSimpleCPU
[all...]
/gem5/src/base/
H A Dpollevent.hh63 void serialize(CheckpointOut &cp) const override; member in class:PollEvent
64 void unserialize(CheckpointIn &cp) override; member in class:PollEvent
/gem5/src/mem/probes/
H A Dmem_footprint.hh62 void regStats() override; member in class:MemFootprintProbe
75 void handleRequest(const ProbePoints::PacketInfo &pkt_info) override; member in class:MemFootprintProbe
/gem5/util/tlm/src/
H A Dsim_control.hh119 SCSlavePort* getSlavePort(const std::string& name) override; member in class:Gem5SystemC::Gem5SimControl
120 SCMasterPort* getMasterPort(const std::string& name) override; member in class:Gem5SystemC::Gem5SimControl
/gem5/src/arch/sparc/insts/
H A Dblockmem.hh70 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::BlockMemMicro
85 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::BlockMemImmMicro
/gem5/src/arch/mips/
H A Dinterrupts.hh113 serialize(CheckpointOut &cp) const override
119 unserialize(CheckpointIn &cp) override
/gem5/src/arch/power/insts/
H A Dcondition.hh61 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::CondLogicOp
83 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::CondMoveOp
/gem5/src/dev/ps2/
H A Ddevice.hh59 void serialize(CheckpointOut &cp) const override; member in class:PS2Device
60 void unserialize(CheckpointIn &cp) override; member in class:PS2Device
/gem5/src/mem/qos/
H A Dpolicy.hh66 virtual void regStats() override {};
68 virtual void init() override {};
/gem5/src/dev/net/
H A Detherint.hh63 void bind(Port &peer) override; member in class:EtherInt
64 void unbind() override; member in class:EtherInt

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