Searched refs:index (Results 76 - 100 of 275) sorted by relevance

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/gem5/src/arch/x86/insts/
H A Dmicroregop.hh67 src1(_src1.index()), dest(_dest.index()),
93 src2(_src2.index())
H A Dmicromediaop.hh62 src1(_src1.index()), dest(_dest.index()),
105 src2(_src2.index())
H A Dstatic_inst.hh60 // TODO: As X86 register index definition is highly built on the
104 uint8_t scale, RegIndex index, RegIndex base,
110 if (_destRegIdx[0].index() & IntFoldBit)
141 if (_srcRegIdx[idx].index() & IntFoldBit)
162 if (_srcRegIdx[idx].index() & IntFoldBit)
/gem5/ext/ply/example/hedit/
H A Dhedit.py30 i = t.value.index('H')
/gem5/ext/ply/test/
H A Dlex_hedit.py30 i = t.value.index('H')
/gem5/src/arch/x86/
H A Dcpuid.hh61 uint32_t index, CpuidResult &result);
/gem5/src/mem/ruby/structures/
H A DPrefetcher.hh118 * @return The index of the least recently used stream buffer.
123 void clearNonunitEntry(uint32_t index);
125 //! allocate a new stream buffer at a specific index
127 uint32_t index, const RubyRequestType& type);
130 //! index holds the multiple of the stride this address is.
132 uint32_t &index);
136 uint32_t *hit_table, uint32_t &index, Addr address,
/gem5/ext/systemc/src/tlm_utils/
H A Dinstance_specific_extensions.h63 //Helper to do the index generation for private extensions
119 // non-templatized version with manual index:
120 ispex_base* set_extension(unsigned int index, argument
124 ispex_base* tmp = m_extensions[index];
125 m_extensions[index] = ext;
136 ispex_base* get_extension(unsigned int index) const
138 return m_extensions[index];
141 // Clear extension, the argument is needed to find the right index:
148 // Non-templatized version with manual index
149 void clear_extension(unsigned int index) argument
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/gem5/src/mem/cache/tags/indexing_policies/
H A Dbase.hh85 * Mask out all bits that aren't part of the set index.
119 * @param index An unique index for the entry.
121 void setEntry(ReplaceableEntry* entry, const uint64_t index);
H A Dbase.cc81 BaseIndexingPolicy::setEntry(ReplaceableEntry* entry, const uint64_t index) argument
83 // Calculate set and way from entry index
84 const std::lldiv_t div_result = std::div((long long)index, assoc);
/gem5/src/arch/riscv/
H A Dinterrupts.hh108 post(int int_num, int index) argument
110 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
115 clear(int int_num, int index) argument
117 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
/gem5/src/cpu/o3/
H A Dregfile.cc142 assert(intRegIds[reg_idx].index() == reg_idx);
149 assert(floatRegIds[reg_idx].index() == reg_idx);
156 assert(vecRegIds[reg_idx].index() == reg_idx);
159 elemIdx].index() == reg_idx);
175 assert(vecPredRegIds[reg_idx].index() == reg_idx);
182 assert(ccRegIds[reg_idx].index() == reg_idx);
192 auto idx = reg->index();
228 return &vecRegIds[reg->index()];
230 return &vecElemIds[reg->index() * NumVecElemPerVecReg +
/gem5/src/gpu-compute/
H A Dtlb_coalescer.hh161 index(_index) { }
165 int index; member in class:TLBCoalescer::CpuSidePort
188 index(_index) { }
194 int index; member in class:TLBCoalescer::MemSidePort
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc646 value_lo = thread->readIntReg(it->index);
650 value_lo = thread->readFloatReg(it->index * 4);
652 value_lo = thread->readFloatReg(it->index);
656 value_lo = thread->readFloatReg(it->index * 4) |
657 (uint64_t) thread->readFloatReg(it->index * 4 + 1) <<
660 value_lo = thread->readFloatReg(it->index * 2) |
661 (uint64_t) thread->readFloatReg(it->index * 2 + 1) <<
667 value_lo = thread->readFloatReg(it->index * 4) |
668 (uint64_t) thread->readFloatReg(it->index * 4 + 1) <<
670 value_hi = thread->readFloatReg(it->index *
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/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/
H A Dtlm_gp.h75 // contruction time. my_extension::ID will hold the unique index in the
512 /* automatically locate the appropriate index in the array. */
527 // non-templatized version with manual index:
528 tlm_extension_base* set_extension(unsigned int index, argument
531 tlm_extension_base* tmp = m_extensions[index];
532 m_extensions[index] = ext;
543 // non-templatized version with manual index:
544 tlm_extension_base* set_auto_extension(unsigned int index, argument
547 tlm_extension_base* tmp = m_extensions[index];
548 m_extensions[index]
605 clear_extension(unsigned int index) argument
610 release_extension(unsigned int index) argument
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/gem5/src/mem/
H A Dstack_dist_calc.cc48 : index(0),
79 // each map entry contains an index and a node
124 "Error in sum left of level %ul, node index %ull, "
128 "Error in sum right of level %ul, node index %ull, "
243 // index%2 == 0 (i.e. every alternate cycle)
245 // OP1. moving the root node one layer up if index counter
254 if (isPowerOf2(index)) {
255 // OP1. moving the root node one layer up if index counter
257 // If index counter crosses a power of 2, then add a
310 // At layer 1 a new INode is added whenever index
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/gem5/configs/example/
H A Dread_config.py139 def __init__(self, object_name, port_name, index):
142 self.index = index
147 object_name, port_name, whole_index, index = m.groups()
148 if index is not None:
149 index = int(index)
151 index = 0
153 return PortConnection(object_name, port_name, index)
156 return '%s.%s[%d]' % (self.object_name, self.port_name, self.index)
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/gem5/configs/boot/
H A Dbbench-ics.rcS26 am start -a android.intent.action.VIEW -d file:///data/bbench/index.html -t application/x-webarchive-xml
/gem5/util/minorview/
H A Dparse.py94 """parse a string of the form "(index,value),(index,value)..."
95 into a list of index, value pairs"""
101 index, value = pair
102 ret.append((int(index), value))
/gem5/src/mem/ruby/common/
H A DHistogram.hh56 uint64_t getData(int index) const { return m_data[index]; }
/gem5/src/arch/sparc/insts/
H A Dmem.cc51 if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
78 if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
H A Dpriv.cc72 if (_srcRegIdx[0].index() != 0) {
92 if (_srcRegIdx[0].index() != 0) {
/gem5/src/mem/cache/prefetch/
H A Dsbooe.hh105 unsigned int index; member in struct:SBOOEPrefetcher::Sandbox
110 : sandboxScore(0), lateScore(0), index(0), stride(_stride)
/gem5/src/cpu/
H A Dreg_class.hh74 /** Register ID: describe an architectural register with its class and index.
75 * This structure is used instead of just the register index to disambiguate
77 * index 3 is represented by Regid(IntRegClass, 3).
101 "Creating vector physical index w/o element index");
104 "Creating non-vector physical index w/ element index");
109 return regClass == that.classValue() && regIdx == that.index()
123 regIdx < that.index() ||
124 (regIdx == that.index()
179 const RegIndex& index() const { return regIdx; } function in class:RegId
180 RegIndex& index() { return regIdx; } function in class:RegId
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/gem5/src/dev/x86/
H A Di82094aa.cc144 int index = (offset - 0x10) / 2; local
146 redirTable[index].topDW = value;
147 redirTable[index].topReserved = 0;
149 redirTable[index].bottomDW = value;
150 redirTable[index].bottomReserved = 0;
170 int index = (offset - 0x10) / 2; local
172 result = redirTable[index].topDW;
174 result = redirTable[index].bottomDW;

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