Searched refs:front (Results 26 - 50 of 105) sorted by relevance

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/gem5/src/systemc/tests/include/
H A DSimpleATTarget2.h133 transaction_type* trans = mResponseQueue.front();
157 mResponseQueue.front()->release();
/gem5/ext/sst/
H A DExtSlave.cc72 link->sendInitData(initPackets->front());
194 while (blocked() && sendTimingResp(respQ.front())) {
/gem5/src/cpu/checker/
H A Dcpu_impl.hh107 inst = instList.front();
137 (instList.front()->seqNum != completed_inst->seqNum) : 0)) {
156 if (!instList.front()->isCompleted()) {
159 inst = instList.front();
433 } else if (instList.front()->isCompleted()) {
435 unverifiedInst = instList.front();
498 checker_val = result.front();
552 int misc_reg_idx = miscRegIdxs.front();
/gem5/src/mem/
H A Dsimple_mem.cc171 // re-order in front of some existing packet with the same
208 DeferredPacket deferred_pkt = packetQueue.front();
221 std::max(packetQueue.front().tick, curTick()), true);
H A Ddramsim2.cc111 bool success = port.sendTimingResp(responseQueue.front());
300 PacketPtr pkt = p->second.front();
/gem5/src/mem/ruby/network/
H A DMessageBuffer.hh71 MsgPtr m = m_prio_heap.front();
100 const MsgPtr &peekMsgPtr() const { return m_prio_heap.front(); }
/gem5/src/mem/cache/
H A Dmshr_queue.cc65 MSHR *mshr = freeList.front();
113 * @ todo might want to add rerequests to front of pending list for
H A Dmshr.cc278 assert(target->matchBlockAddr(targets.front().pkt, blkSize));
347 PacketPtr tgt_pkt = targets.front().pkt;
413 PacketPtr tgt_pkt = targets.front().pkt;
562 order = targets.front().order;
563 readyTime = std::max(curTick(), targets.front().readyTime);
H A Dwrite_queue_entry.cc117 assert(target->matchBlockAddr(targets.front().pkt, blkSize));
H A Dmshr.hh339 PacketPtr pkt = targets.front().pkt;
477 return &targets.front();
H A Dnoncoherent_cache.cc104 PacketPtr wb_pkt = writebacks.front();
114 PacketPtr wb_pkt = writebacks.front();
/gem5/src/mem/qos/
H A Dq_policy.cc93 if (toServe.front() == m_id) {
97 // move toServe front to back
/gem5/src/cpu/minor/
H A Dexecute.cc198 const ForwardInstData &head = inputBuffer[tid].front();
200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
1034 * We do this by looping on the front of the inFlightInsts queue for as
1068 *(ex_info.inFlightInsts->front().inst),
1082 *(ex_info.inFlightInsts->front().inst));
1085 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1168 ex_info.inFUMemInsts->front().inst;
1170 const MinorDynInstPtr &fu_inst = fu->front().inst;
1208 funcUnits[inst->fuIndex]->front();
1341 ex_info.inFUMemInsts->front()
[all...]
H A Dfetch1.cc285 if (!requests.empty() && requests.front() != request) {
286 DPRINTF(Fetch, "Fetch not at front of requests queue, can't"
324 assert(!requests.empty() && requests.front() == request);
367 tryToSendToTransfers(requests.front());
384 delete queue.front();
460 FetchRequestPtr retryRequest = requests.front();
668 transfers.front()->isComplete())
670 Fetch1::FetchRequestPtr response = transfers.front();
H A Ddecode.cc86 const ForwardInstData &head = inputBuffer[tid].front();
88 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
/gem5/src/base/
H A Dcircular_queue.test.cc67 * of front() and back() (head an tail). Since we are just
68 * adding elements and not removing them, we expect the front
78 ASSERT_EQ(cq.front(), first_element);
83 ASSERT_EQ(cq.front(), first_element);
170 * values of (front() and back())
183 ASSERT_EQ(*(cq.begin()), cq.front());
/gem5/src/gpu-compute/
H A Dlds_state.cc282 while (!returnQueue.empty() && returnQueue.front().first <= now) {
283 PacketPtr packet = returnQueue.front().second;
309 Tick next = returnQueue.front().first;
H A Dwavefront.cc187 GPUDynInstPtr ii = instructionBuffer.front();
202 GPUDynInstPtr ii = instructionBuffer.front();
215 GPUDynInstPtr ii = instructionBuffer.front();
228 GPUDynInstPtr ii = instructionBuffer.front();
241 GPUDynInstPtr ii = instructionBuffer.front();
254 GPUDynInstPtr ii = instructionBuffer.front();
325 GPUDynInstPtr ii = instructionBuffer.front();
545 GPUDynInstPtr ii = instructionBuffer.front();
653 GPUDynInstPtr ii = instructionBuffer.front();
/gem5/src/dev/
H A Ddma_device.cc224 PacketPtr pkt = transmitList.front();
268 PacketPtr pkt = transmitList.front();
433 DmaDoneEventUPtr event(std::move(freeRequests.front()));
462 while (!pendingRequests.empty() && pendingRequests.front()->done()) {
464 DmaDoneEventUPtr event(std::move(pendingRequests.front()));
/gem5/src/systemc/tests/tlm/multi_sockets/
H A DMultiSocketSimpleSwitchAT.h251 sc_assert(m_pendingReqs[connInfo->fwID].front()==&trans);
255 initiatorNBTransport_core(*m_pendingReqs[connInfo->fwID].front(), ph, t,connInfo->fwID);
317 m_bwPEQ.notify(*m_pendingResps[connInfo->bwID].front(),ph,t);
/gem5/src/dev/net/
H A Detherswitch.cc187 if (!sendPacket(outputFifo.front())) {
192 DPRINTF(Ethernet, "packet sent: len=%d\n", outputFifo.front()->length);
205 Tick delay = (Tick)ceil(((double)outputFifo.front()->simLength
H A Detherswitch.hh154 EthPacketPtr front() { return fifo.begin()->packet; } function in class:EtherSwitch::Interface::PortFifo
/gem5/src/mem/cache/prefetch/
H A Dsbooe.cc113 latencyBufferSum -= latencyBuffer.front();
H A Dqueued.hh192 return pfq.empty() ? MaxTick : pfq.front().tick;
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh655 assert(loadQueue.front().valid());
658 loadQueue.front().instruction()->pcState());
660 loadQueue.front().clear();
670 assert(loads == 0 || loadQueue.front().valid());
672 while (loads != 0 && loadQueue.front().instruction()->seqNum
682 assert(stores == 0 || storeQueue.front().valid());
1008 storeQueue.front().clear();
1011 } while (storeQueue.front().completed() &&

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