Searched refs:access (Results 51 - 54 of 54) sorted by relevance
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| /gem5/src/mem/cache/ |
| H A D | base.cc | 225 // just as the value of lat overriden by access(), which calls
233 // still relying on it; if the block is found in access(),
348 // access() will set the lat value.
349 satisfied = access(pkt, blk, lat, writebacks);
359 // The latency charged is just the value set by the access() function.
548 // access in timing mode
551 // to access.
556 bool satisfied = access(pkt, blk, lat, writebacks);
570 // handle writebacks resulting from the access here to ensure they
984 // A tag-only access ha
1024 BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, function in class:BaseCache
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| /gem5/src/mem/ |
| H A D | dram_ctrl.cc | 272 // do the actual memory access and turn the packet into a response
273 access(pkt);
922 // do the actual memory access which also turns the packet into a
924 access(pkt);
928 // access already turned the packet into a response
966 // auto-precharged, and when this access is forced to
984 // The next access has to respect tRAS for this bank
1105 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1125 // Determine the access latency and update the bank state
1197 // Save rank of current access
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| /gem5/src/sim/ |
| H A D | syscall_emul.cc | 1162 int result = access(path.c_str(), mode);
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| H A D | syscall_emul.hh | 315 /// Target access() handler
859 * 2) Try to handle the access using 'special_paths'. Some special_paths
2143 if (access(path.c_str(), F_OK) == -1)
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