Lines Matching refs:access
272 // do the actual memory access and turn the packet into a response
273 access(pkt);
922 // do the actual memory access which also turns the packet into a
924 access(pkt);
928 // access already turned the packet into a response
966 // auto-precharged, and when this access is forced to
984 // The next access has to respect tRAS for this bank
1105 DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
1125 // Determine the access latency and update the bank state
1197 // Save rank of current access
1287 // if this access should use auto-precharge, then we are
2592 .desc("Average memory access latency per DRAM burst")
2805 .desc("Per-master read total memory access latency")
2809 .desc("Per-master read average memory access latency")
2818 .desc("Per-master write total memory access latency")
2822 .desc("Per-master write average memory access latency")