Searched hist:7321 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/riscv/insts/
H A Dstandard.cc12438:c7514a2a926d Thu Dec 14 23:22:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Don't crash when printing unknown CSRs

This patch fixes a potential crash if an unnamed CSR is accessed and
debug flags are enabled that print disassembly. Unknown CSRs will be
identified as "??" followed by the address that was used.

Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Reviewed-on: https://gem5-review.googlesource.com/7321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
/gem5/src/arch/arm/isa/decoder/
H A Dthumb.isa7321:d0fdf3452086 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.
H A Darm.isa7321:d0fdf3452086 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.
/gem5/src/arch/arm/isa/formats/
H A Dfp.isa7321:d0fdf3452086 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.

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