Searched hist:6621 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/dev/ | ||
| H A D | mc146818.cc | 6621:835a99bdab10 Fri Aug 21 02:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> RTC: Make calls to writeData update the RTCs internal representation of time. |
| /gem5/src/arch/arm/ | ||
| H A D | faults.hh | 12402:a90842ce2303 Fri Dec 01 08:24:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Hyp routed undef fault need to change its syndrome If undefined instruction has to be routed to EL2, the HSR register must change the HSR.EC and HSR.ISS accordingly, which means not using the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0) Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6621 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | faults.cc | 12402:a90842ce2303 Fri Dec 01 08:24:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Hyp routed undef fault need to change its syndrome If undefined instruction has to be routed to EL2, the HSR register must change the HSR.EC and HSR.ISS accordingly, which means not using the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0) Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6621 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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